Tips for reducing resonance and SSN.

Fast interfaces and switching speeds are becoming commonplace, and with them comes increased noise, amplifying any problems within the power delivery network. Products today are the direct result of the fast signal capabilities in current technology, making it impossible to eliminate noise. This noise can be seen in the form of simultaneous switching noise, which resonates and can combine to destroy the voltage signal and collapse the signal eye. Therefore, the only viable option is to mitigate the noise via containment.

Ground is the point from which every measurement is evaluated. Therefore, any variation will affect timing and voltage. Every signal switching on the board, whether slow or fast, contributes to noise on the power and ground planes. This “ground bounce” is commonly referred to as simultaneous switching noise (SSN) and is essentially crosstalk on the ground (FIGURE 1).

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In PDN design, maintain a low impedance over a range of frequencies, as opposed to just one.

Achieving a robust and functioning power distribution network isn’t difficult if we provide both the capacity and responsiveness needed at each device. Previous columns addressed capacity concerns, discussing the need for sufficient copper (or an alternative conductor) between a voltage source and any load depending on it for its supply. Here, we build on those and examine what’s required to maintain that network at a steady voltage. This relies on sufficient “energy stores” and the conduction paths needed to deliver charge quickly to any location on the board experiencing “instantaneous demand.”

DC vs. AC (aka static vs. transient). Historically, nearly all power conversations pertaining to printed circuit boards have been lumped into two categories, with the terms “power DC” and “power AC” emerging as almost standard terminology. Power DC is understandable as it addresses PDN capacity issues associated with inadequate copper.

Our experience with DC analysis reveals the simulation process, once thought to be complex, is nothing more than the visualization of Ohm’s law. With voltage defined in our DC supplies, and current by the operating requirements of each load, we found tools could readily calculate the resistance by extracting the geometry of the conductors. Using these resistance models in conjunction with the current needs of each IC (defined by their electrical specifications), it is easy to predict the DC voltage available in each chip given its distance from the source. This makes the cumulative resistance from the source the determining factor defining the DC performance each IC experienced.

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