White Papers

High-Speed Constraint Values and PCB Layout MethodsPfeil secondedition web

by Charles Pfeil (Forward by Rick Hartley)


How to Receive Your Copy

To download your free copy of this new e-book and the Constraint Value Calculator today, please submit your name and a valid email address. Be sure to click the Request Download Link button. A link to the downloads will be emailed to the address provided.



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About the Book

High-Speed Constraint Values and PCB Layout Methods encompasses lessons learned from Charles Pfeil’s five decades in PCB design. It covers critical length, reference planes, timing, skew, crosstalk, coupling, vias, and routing. The book provides the underlying equations and specializes in practical solutions for real-life signal problems.

Constraint Value Calculator

This download includes the Constraint Value Calculator.

The Constraint Value Calculator is an Excel-based worksheet developed by Charles Pfeil. The faster the edge rate, the more likely the signal will have timing, crosstalk and signal integrity problems. Also, the constraint values become tighter as the edge rate increases. As such, the Constraint Value Calculator provides rules with appropriate constraint values for high-speed designs. It includes options for edge rate, dielectric constant, and height between the layers to determine constraint values.

About the Author

Charles Pfeil 2013

Charles Pfeil has spent over 50 years in the PCB industry as a designer, owner of a service bureau, and in engineering management and product definition roles at Racal-Redac, ASI, Cadence, PADS, VeriBest, Mentor Graphics, and Altium.

Most of his career was at Mentor Graphics, where he was a software architect focused on advanced development of PCB design tools. He was the original product architect of Expedition PCB, and an inventor of Team PCB, XtremePCB, XtremeAR, and the Sketch Router. He previously authored BGA Breakouts and Routing.

He was inducted into The Dieter Bergman Hall of Fame for PCB Design in 2013.

Over the last few decades, in-circuit test (ICT) has been integral to the growth of the electronics industry. Now though, because of rapidly accelerating speeds and new levels of complexity, chips, circuit boards and systems are moving beyond the reach of the intrusive probes and bedof-nails fixtures that ICT depends on. This white paper explains the technical and economic factors that are contributing to the gradual but inevitable demise of ICT and how non-intrusive board test (NBT) has emerged as a more cost-effective and thorough test technology for the manufacturing floor. Certainly ICT will continue to have its place, albeit current trends indicate it will soon be relegated to special case testing or for testing rudimentary circuit board designs. Simply stated, electronics manufacturers (original equipment manufacturers or original design manufacturers) are finding it increasingly difficult to make a credible business case for ICT, especially when NBT offers better test coverage and a lower cost structure.


The introduction of fine-line technologies to printed circuit board design and manufacture has stretched most previous automatic routing algorithms to the limit. A different approach designed specifically to meet the present needs is detailed.


When designing LED-based lighting systems, engineers need to understand LED lumen maintenance and mortality in similar terms to those used when designing with conventional light sources. However, comparable data has been nearly impossible to find. In addition, designers need extra information to predict the lifetime of LEDs under a variety of operating conditions. A number of techniques to predict LED lifetimes have been proposed, but these have not been sufficient to generate the clear and unambiguous data that lighting engineers can use easily. This white paper provides lighting designers with an understanding of a new tool introduced by Philips Lumileds Lighting that simplifies the process, allowing flexibility in design options. This one tool provides designers with information that they need to make decisions about product lifetimes, driver constraints, number of LEDs required, and thermal management.

Link here


Executive Summary

Factors like jitter, inter-symbol interference (ISI), crosstalk and others can create havoc on the signal integrity of high-speed serdes and memory channels, making maximum bus speeds difficult to achieve in practice. Compounding this predicament is the fact that channel speeds keep increasing from one generation bus technology to the next. With each step upward to a higher speed and higher signaling frequencies, a serdes or memory bus becomes more susceptible to distortions and anomalies which can effectively disrupt bus traffic and stall system throughput. For serdes buses like PCI Express™ , Serial ATA, USB, Intel’s QuickPath Interconnect (QPI) and memory buses like DDR, the higher the frequency of the signaling, the more susceptible the interconnect becomes to errors, re-transmissions and other anomalies.

To avoid potential problems with high-frequency bus traffic the signal integrity on the bus must be validated during each of the major phases of a system’s life cycle, including design/development, manufacturing and as an installed system in the field. If the signal integrity on a serdes channel is not what it should be, steps should be taken to correct the problem and improve system performance.

Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult as the limitations of legacy probe-based test equipment have become more obvious in recent years. Now though, non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more costeffective and deliver observed signal integrity data. These methods provide soft access to hard data. In addition, industry specifications like the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instrumentation are emerging to simplify and streamline the adoption of signal integrity validation techniques based on embedded instruments.

By Bob Burns, National Sales & Marketing
Printed Circuits Inc.



Greater acceptance of rigid flex circuit boards in medical and other high reliability electronic packaging has created a demand for UL recognition for flame rated packaging, primarily to meet product liability insurance carrier requirements. 

The Problem

The difficulty lies in getting a UL rating on rigid flex constructions due to the overwhelming number of configurations that must be represented in the test vehicles.

Previous Options

Designers and fabricators wishing to resolve this issue have used two primary methods – specifying UL rated materials and/or submitting individual constructions for UL recognition.  The first solution does not meet the requirements of UL or insurance carriers, and the second solution is limited, expensive and time consuming.

The Printed Circuits, Inc. Solution

Printed Circuits, Inc. has undertaken the task of obtaining UL 94 V-0 flame rating for a large sampling of popular constructions representing most of the possibilities that rigid flex designers would use.


PWB designers and buyers now have a source for fully compliant UL 94 V-0 rated boards to satisfy their insurance carrier’s requirements.
Printed Circuits UL certifications eliminate the cost and time required to test individual boards – most popular constructions can be certified immediately.


Printed Circuits, Inc.’s UL recognition eliminates the cost and time required for electronics designers and buyers to qualify their rigid flex boards.

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