White Papers

When designing LED-based lighting systems, engineers need to understand LED lumen maintenance and mortality in similar terms to those used when designing with conventional light sources. However, comparable data has been nearly impossible to find. In addition, designers need extra information to predict the lifetime of LEDs under a variety of operating conditions. A number of techniques to predict LED lifetimes have been proposed, but these have not been sufficient to generate the clear and unambiguous data that lighting engineers can use easily. This white paper provides lighting designers with an understanding of a new tool introduced by Philips Lumileds Lighting that simplifies the process, allowing flexibility in design options. This one tool provides designers with information that they need to make decisions about product lifetimes, driver constraints, number of LEDs required, and thermal management.

Link here


Executive Summary

Factors like jitter, inter-symbol interference (ISI), crosstalk and others can create havoc on the signal integrity of high-speed serdes and memory channels, making maximum bus speeds difficult to achieve in practice. Compounding this predicament is the fact that channel speeds keep increasing from one generation bus technology to the next. With each step upward to a higher speed and higher signaling frequencies, a serdes or memory bus becomes more susceptible to distortions and anomalies which can effectively disrupt bus traffic and stall system throughput. For serdes buses like PCI Express™ , Serial ATA, USB, Intel’s QuickPath Interconnect (QPI) and memory buses like DDR, the higher the frequency of the signaling, the more susceptible the interconnect becomes to errors, re-transmissions and other anomalies.

To avoid potential problems with high-frequency bus traffic the signal integrity on the bus must be validated during each of the major phases of a system’s life cycle, including design/development, manufacturing and as an installed system in the field. If the signal integrity on a serdes channel is not what it should be, steps should be taken to correct the problem and improve system performance.

Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult as the limitations of legacy probe-based test equipment have become more obvious in recent years. Now though, non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more costeffective and deliver observed signal integrity data. These methods provide soft access to hard data. In addition, industry specifications like the IEEE P1687 Internal JTAG (IJTAG) standard for embedded instrumentation are emerging to simplify and streamline the adoption of signal integrity validation techniques based on embedded instruments.

By Bob Burns, National Sales & Marketing
Printed Circuits Inc.



Greater acceptance of rigid flex circuit boards in medical and other high reliability electronic packaging has created a demand for UL recognition for flame rated packaging, primarily to meet product liability insurance carrier requirements. 

The Problem

The difficulty lies in getting a UL rating on rigid flex constructions due to the overwhelming number of configurations that must be represented in the test vehicles.

Previous Options

Designers and fabricators wishing to resolve this issue have used two primary methods – specifying UL rated materials and/or submitting individual constructions for UL recognition.  The first solution does not meet the requirements of UL or insurance carriers, and the second solution is limited, expensive and time consuming.

The Printed Circuits, Inc. Solution

Printed Circuits, Inc. has undertaken the task of obtaining UL 94 V-0 flame rating for a large sampling of popular constructions representing most of the possibilities that rigid flex designers would use.


PWB designers and buyers now have a source for fully compliant UL 94 V-0 rated boards to satisfy their insurance carrier’s requirements.
Printed Circuits UL certifications eliminate the cost and time required to test individual boards – most popular constructions can be certified immediately.


Printed Circuits, Inc.’s UL recognition eliminates the cost and time required for electronics designers and buyers to qualify their rigid flex boards.

TI OMAP4xxx POP SMT Design Guideline


Package Introduction
OMAP4 SMT Process sharing
Stencil/PCB design guide
Memory chip flux/solder dipping in 1-step mounting
The example of Pick & Place machine condition setting
Reflow profile recommendation
SMT experiment examples
Q& A


Voltage Derating Rules for Solid Tantalum and Niobium Capacitors

Abstract: For many years, whenever people have asked tantalum capacitor manufacturers for general recommendations on using their product, the consensus was "a minimum of 50% voltage derating should be applied." This rule of thumb has since become the most prevalent design guideline for tantalum technology. This paper revisits this statement and explains, given an understanding of the application, why this is not necessarily the case.

With the recent introduction of niobium and niobium oxide capacitor technologies, the derating discussion has been extended to these capacitor families also.

Design for Manufacturing (DFM): Verifying Component Selection

by New Age Technologies

Abstract: When qualifying any component for a RoHS design or conversion, it is important to document in the item
master record what processes the component can withstand and how many heat cycles it can endure. A low
ESR capacitor in an 1812 package may indeed be RoHS compliant but only be RoHS process compatible to
certain processes. The equipment used to process the design must also be taken into account. Re-flow ovens
that were well suited for lead processing may limit the options available for RoHS processing. Through-hole
component selection and thermal relief is much more critical with RoHS processing than it was with SN63.
It is critical to qualify each component or family of components to a defined process or set of processes to
avoid quality and reliability issues.

Published: 2008

High Speed PCB Design / Ride the Wave Workshop

by Ansoft

Post route analysis of a high-speed printed circuit board design and design/analysis for power delivery systems (PDS).

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