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IPC-2152 is an important baseline for determining current carrying capacity, but further work must be done for individual applications.

In response to recent chatter about IPC-2152 in multiple online articles, I believed it necessary to reiterate the purpose behind the IPC design standard for sizing electrical traces.

IPC 1-10b is a task group of volunteers from several companies in the electronics industry. I was task group chairman from 1999 to 2016. We designed test boards and wrote IPC-2152, Standard for Determining Current-Carrying Capacity in Printed Board Design. The standard is intended to describe the test data used to define trace heating in a specific configuration through conductor sizing design charts. Testing was performed following IPC-TM-650, method 2.5.4.1A, “Conductor Temperature Rise Due to Current Changes in Conductors.” The design charts are only applicable to that configuration. Designs with different board sizes, thicknesses, and materials, including copper planes – when mounted by bolted fasteners or wedgelocks – have different trace temperatures for an applied current. People and corporations have to create their own charts if they want to have an accurate temperature for a given trace size and applied current. The information included in IPC-2152 provides that information. (Accurate temperatures can only occur from a design chart if that chart represents the specific technology.)

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Summit Interconnect’s chief executive explains the PCB fabricator’s latest buy.

Summit Interconnect in May announced the acquisition of fellow printed circuit board fabricator Royal Circuit Solutions for an undisclosed sum.

But while the deal at first glance looks like the latest in a long string of capacity buys for the second-largest fabricator in North America, there is more to it than meets the eye.

For its part, Royal has engineering tools and staff that Summit can leverage to speed its own operations.

Royal also includes an electronics assembly operation, Aurora, CO-based Advanced Assembly. The EMS outfit’s quickturn production capabilities fit well with Summit’s commercial prototype programs. That the fab and assembly sides are integrated adds one more appealing facet to the acquisition.

Summit chief executive Shane Whiteside broke down the latest acquisition in an interview with Mike Buetow.

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A new specification tackles the application and performance of organic solderability preservatives.

After many years of starts, stops and debate, an industry committee has finally developed a standard for organic solderability preservatives (OSPs). IPC-4555, Performance Specification for High Temperature Organic Solderability Preservatives (OSP) for Printed Boards, is out now, and it was a long time coming.

With the electronics industry fully entrenched in lead-free soldering, a standard for OSP is critical. There are more stringent requirements for solder joint reliability, resistance to corrosion, as well as additional requirements related to complex substrate designs.

The development and acceptance of IPC-4555 dispels the myth all OSPs are the same. With circuit boards fabricated around the globe, and small chemical firms attempting to introduce “new OSP processes,” buyers must be aware. Greater solderability requirements – measured as joint strength, paste spreadability and hole fill – and higher temperatures of lead-free soldering have greatly diminished use of conventional (standard substituted benzimidazole-based) OSPs. With the development of third- and fourth-generation organic solderability preservatives based on a novel aryl-phenylimidazole compound, however, OSP has regained its leadership role as a final finish, particularly in Asia and Europe. In addition, the technology shift to bare copper PWBs with selectively plated gold features requires OSPs that do not tarnish or deposit on the gold.


The Genesis of IPC-4555

Input from OEMs, EMS companies, PCB fabricators and chemical suppliers paved the way for the development and acceptance of IPC-4555. Several years ago, an IPC task group attempted to develop a standard governing OSPs. For a multitude of reasons, perhaps lack of understanding, politics, etc., the proposed standard never reached the ballot stage, a requirement for publication. A few years later, a new task group convened to bring an IPC standard for OSP to the industry. TABLE 1 shows the charter of that group.

TABLE 1. IPC-4555 Committee Charter1

7 carano table 1

The charter shaped the work the IPC-4555 task group undertook. The group also recognized the following:

  • OSP (organic solderability preservative) technology is environmentally friendly, provides a coplanar surface, and requires very low equipment maintenance. The process is designed for horizontal, conveyorized processing. However, vertical immersion systems are easily integrated into the printed wiring board fabrication process.
  • Third- and fourth-generation OSP formulations are robust and provide excellent protection against oxidation of the underlying copper through multiple IR reflows under lead-free assembly conditions.
  • Various industry studies and OEM interviews as late as 2020 revealed that well over 55% of the circuit board substrates manufactured (by surface area) are produced with OSP technology. OSP is not going away any time soon. And with increased use of QFNs, IC packaging substrates, BGAs, etc., OSP use will continue to find additional applications.

That said, it is prudent to dispel some of the pervasive OSP myths.

OSP Myths and Truths

Myth #1: “An OSP is an OSP. They are all the same.” This is not only a myth; it is categorically false. The world of lead-free assembly has separated the low-level OSP processes from those formulated and engineered for optimum performance. A simple look at formulations and molecular structures provides further insight into OSP technology. Part of the confusion stems from the name of the organic compound that is the main ingredient in OSP processes: azole. These five letters are attached to various formulations and often appear ideal for solderability preservation to the uninformed. As an example, conventional OSP processes based on long-chain alkylimidazole compounds and substituted benzimidazole compounds functioned adequately to protect the bare copper. These worked well for lead-based assembly, which takes place at lower temperatures. However, higher temperatures of lead-free assembly (including longer dwell times), along with a multitude of lead-free solder pastes, exposed many of these lower-level azole processes. Ushering a new class of azole molecules based on complex reaction products, known collectively as aryl-phenylimidazole, these compounds are very stable up to 350°C. This formulation provides higher heat stability and can easily withstand the peak temperature of reflow for typical lead-free solders.  

Myth #2: “One can always improve solderability of an OSP by increasing the OSP thickness over the copper surface.” Again, this is not true. The critical nature of an OSP is the coating should be as uniform as possible over the copper surface. In addition, excessively thick OSP films make it more difficult for no-clean fluxes and solder pastes to dissolve the OSP coating during the assembly process. When this occurs, the solder paste spread may not complete wet-out over the SMT pad.

The team addressed these issues in IPC-4555. Thickness ranges were not set, as they sometimes are in the metal finish type standards. Instead, it is left to the expertise of the individual OSP suppliers to provide the optimum thickness ranges for solderability performance. Thickness is not critical. Rather, it is the uniformity of the OSP over the base copper and the OSP film’s ability to reduce oxygen penetration to the copper.  

Myth #3: “OSP technology does not have sufficient lubricity to function as a coating for press-fit.” This is also a myth. The IPC-4555 task group addressed press-fit with multiple stakeholders from connector and OEM end-users. OSP technology is in widespread use for press-fit applications. The published standard now addresses press-fit as follows:

Press-fit (inserted pin). Press-fit requirements shall meet Telcordia GR-1217-CORE and IEC 60352-5, Solderless Connections – Part 5: Press-In Connections – General Requirements. Also refer to IPC-9797 (evaluation guidance document).1

Additional Information

A major challenge for OSP is providing a printed wiring board finish that will maintain solderability and provide a highly reliable joint with lead-free solders. This is no easy task. A multitude of different lead-free formulations and interactions with fluxes influence reliability. The surface finish must foster the optimum wetting and intermetallic formation under multiple thermal excursions and higher soldering temperatures required for lead-free solders. How will the surface finish react to these greater temperature and time stresses? What will be the effect on solder paste spread and hole fill after thermal excursion? This is the critical success factor/integrity of the final finish and its ability to preserve solderability. Certainly the end-user often specifies the finish due to personal preference, history, cost, reliability, fit with certain PWB designs, and so on. Regardless, a walk through any EMS company will provide the visitor with the full range of finishes, depending on the various requirements of the customer.

The IPC-4555 task group members submitted statistically significant data to support solderability requirements as outlined in the standard. The data further supported that latest generation OSP technology was indeed an excellent finish for complex circuit designs, including BGA substrates, and compatible with many lead-free solder materials and fluxes.

The primary function of OSP is to provide a solderable surface finish capable of providing a coating durability rating of B, per J-STD-003C, Solderability Tests for Printed Boards. Coating durability B is “intended for boards likely to experience multiple soldering processes and/or other process steps using SnPb or Pb-free assembly profiles.”2 This surface finish is suitable for all surface-mount, hybrid and through-hole assembly applications. The solderability requirement is for all OSP-plated SMT features tested to wet with solder covering at least 95% of each feature. It is noted, if a static solder float test is utilized, factors including board thickness, feature hole aspect ratio, number of internal copper planes, etc., will have an impact on solderability testing results. For challenging designs, it is recommended to use the assembly soldering method for solderability testing. For through-hole solderability, the solder shall flow up through the via and wet the pad on the top side of the board (FIGURE 1).

7 carano figure 1

FIGURE 1. PTH solder requirement, per IPC-A-600H.

Review visuals are as shown in IPC-A-600H, Acceptability of Printed Boards.

Storage, Handling and Shelf Life of OSP

No discussion – or a standard – would be complete without a full understanding of the storage, handling and shelf life of OSP-coated circuit boards.

The committee understood shelf life of OSP-coated circuits may not be as long as some metallic-finished boards. That said, IPC-4555 lists the shelf life as a “minimum of six months.” Such coatings have been shown in real-time testing by the IPC-4555 task group to demonstrate a shelf life minimum of six months. With proper storage and handling, OSP coatings have been shown to have a 12-month shelf life.

It is recommended to perform either a classic solderability edge dip/solder float test or a solder paste print and reflow on the assembly production line prior to using OSP-coated product that is older than six months.

Storage and Handling of OSP-Processed PWBs

Before OSP-coated PWBs are packaged, the boards shall be free of moisture, particularly for small vias. The dry boards can then be packaged for shipping to the end-user. Operators should handle the dried boards on the edges and protect hands with impermeable gloves. This is necessary to prevent oils and ionic contamination from affecting the PWB performance. An outer slip sheet made of sulfur-free material should be placed on the top and bottom of the stack. Shrink wrap should be applied to seal the package. Sealed packages can be placed in a box for shipping. Desiccant should be added to the box and the box sealed. End-users should keep boards in the shrink-wrapped package until ready for assembly.  

We finally have an industry-recognized and accepted standard for the use of organic solderability preservatives. This should help level the playing field with respect to the reliability and performance of circuit boards fabricated with OSP finishes. IPC-4555 clearly sets the bar high for anyone wishing to supply or implement OSP finish. 

References
1.    IPC-4555, Performance Specification for High Temperature Organic Solderability Preservatives (OSP) for Printed Boards, April 2022.
2.    J-STD-003C, Solderability Tests for Printed Boards, September 2017.

MICHAEL CARANO is a recognized subject matter expert in printed circuit, semiconductor, surface finishing and medical device industries. His focus is on process control and bring new technologies to market.

A single one can destroy a signal, but predictions with validated models can be made. 

An ideal digital interconnect is a lossless transmission line with characteristic impedance and phase delay flat over the signal bandwidth and termination resistors equal to the characteristic impedance. In such interconnect, bits generated by a transmitter would flow seamlessly into the receiver with no limits on the bit rate. Such a utopian transmission line exists only in our imaginations and textbooks. The physics of our world prohibit it. One way to describe “what happens to the signal on the way to a receiver?” is to use the balance of power that can be written for the passive interconnect as follows:

P_out = P_in - P_absorbed - P_reflected - P_leaked + P_coupled

This is frequency domain over the bandwidth of the signal.1 P_out is the power delivered to the receiver, and P_in is the power delivered by transmitter to the interconnect. All other terms in the balance of power equation describe the signal distortion. The formula above expresses all we need to know about the interconnects. (It should be “cast in granite.”). As they say, “a formula is worth a thousand words,” almost literally in this case. To understand it, imagine the interconnect system as a multiport with the transmitter at port 1, receiver at port 2 and multiple other ports for links coupled to the link connecting port 1 and 2 and terminations to real impedance (not necessarily identical at all ports) – something like this below, together with the definition of waves and scattering parameters (or S-parameters):

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