To increase signal quality, match the impedance, capacitance and inductance of all areas of the signal path.
In PCB design and fabrication, possibly the most frequently used, yet least understood, term is impedance.
Most of us have seen the buzzwords that accompany it: impedance Zo, 50Ω, 10%, balanced lines, microstrip, stripline ground plane, dielectric loss, dielectric constant, and others. What do they mean?
In this first of a two-part column, we’ll start by defining them in common terms for the novice. By the end, a few more people might make better sense of what is happening inside the circuit board. The second half will take a more thorough look at impedance.
First, why do we need impedance specifications? When a fast rise time signal (i.e., a 100MHz to 10GHz or higher pulse) travels down a PCB trace without impedance matching, not much of any use comes out the other end of the trace. What does come out is only a percentage of the original signal, with rounded-off edges and ringing on the trailing edge.
To continue reading, please log in or register using the link in the upper right corner of the page.
Read more: What is Impedance, and How Does It Work?
A walkthrough shows why you can’t “guess” success.
When a customer learns their much-needed PCB job has inexplicably gone into the dreaded “hold” basket, the instinctive response is indignation. Let’s take a moment to examine the possible reasons. After all, the fabricator doesn’t want an unhappy customer, nor a pause in work volume. Yet, a great deal of precise data is needed to build a printed circuit board. As layer count and complexity increase, so does the volume of correct information needed by the fabricator to properly manufacture the job. If some necessary data are missing, the CAM operator will hand the file back to sales to sort out the problems.
The one steadfast rule all PCB manufacturing facilities hold dear is “we don’t guess.” Never. Break that rule and the consequences will bite back hard. To ensure no one is guessing, every question must be answered. If you failed to specify a tolerance on a set of holes, the job will go on temporary hold until the CAM operator can get a suitable answer. If you have an electrical short between ground power layers due to a misplaced via, the job goes back to sales to sort out. When a job is on hold for a serious problem, the result can be days of delay. If there are one or two small issues, however, in many instances the CAM operator or sales will call and sort it out. They might be able to move a trace or two to prevent a short, for example, or change a pad size to correct a problem with an annual ring that is too small. However, the CAM operator must meet a quota of jobs each day to keep the manufacturing facility fully loaded. They do not have an abundance of time to fix a multitude of problems in an individual customer’s data. Other jobs are waiting! In that case, the CAM operator hands the file back to sales to reject the data. The customer can then fix it and resubmit it through the whole process of price quote, DRC (design rule check) and setup.
To continue reading, please log in or register using the link in the upper right corner of the page.
Warping of flat or planar printed circuit boards is a significant yet common problem when manufacturing and assembling PCBs.
Warpage can prevent pick-and-place machines from accurately placing components. Warpage can cause the lead-free wave solder machine to pick up solder and flood the board with solder. Even worse, a warped printed circuit may not fit in the case or cause problems with automated handling equipment (buffers, etc.).
A few items cause warpage, all known and preventable. The primary reason why a PCB will warp is uneven or imbalanced copper percentages in different layers. When a design is presented to a PCB manufacturer, the fabricator will run a check of the percentage of copper on each layer. This is to ensure the design is balanced; i.e., the copper plane percentages are even about the center. Consider, for instance, a typical 8-layer PCB. A copper power plane would be on layers 4 and 5 and signal layers on the remaining layers. The innerlayer 4-5 has an almost full copper percentage on both sides. The remaining layers are low-copper-percentage signal layers. The stresses locked in by lamination will even out or equilibrate.
To continue reading, please log in or register using the link in the upper right corner of the page.
An hour-by-hour look at the quickturn fabrication process.
We were presented with a challenge: Is it possible to build 10 prototype 12-layer boards in 72 hours? It wasn’t a rhetorical question; a customer really wanted just such an order. So, with time at a premium, our engineers put their heads together and created a “plan of attack” that optimized all resources. One key to success is performing a number of the steps in sequence as needed, so panels are ready when they are required. We’ll describe the procedure hour-by-hour as follows:
Hour 1: The CAM operator runs a DRC (design rule check) process and accepts or rejects the data files. If a problem exists, they contact the buyer to work out a solution; e.g., if two traces are too close, and one needs to be moved. Once the data file is accepted, the next action is to set up the innerlayers.
To continue reading, please log in or register using the link in the upper right corner of the page.
