“How to CE Mark Your Product”
Abstract: CE marking your new product is not as difficult or as expensive as one might think. Many entrepreneurs worry that the process will drain them of cash, bury them in regulation and paperwork and leave them exposed if they do not do it exactly right. If you are clever about it, it is none of these.
The first thing to understand is that there is no such thing as a perfectly certified CE product. The amount of time you invest in it is up to you, but the responsibility for making sure you have invested enough is also up to you. It is a self-certification process. It will be necessary to make sure the administration is strictly controlled. It must be issue controlled and properly backed up. An enormous amount of money can also be saved by designing for EMC properly and going to the EMC test house properly prepared. (Company white paper, July 2013)
“Guidelines for Ensuring PCB Manufacturability”
Abstract: This white paper discusses ways to troubleshoot a number of common problems in the design-to-manufacture process. It explores a number of straightforward ways to increase the manufacturability of PCBs. It looks at such issues as the mismatch between DfM rules and component footprints, and at integrating backend DfM tools. (Company white paper, January 2014)
“How to Patent a Product”
Abstract: If you have an idea and are wondering whether a patent is appropriate, there are three tests to apply to confirm that the idea is patentable: 1. It must be novel. 2. It must be commercially applicable. 3. It must have an inventive step. This white paper gives an overview of the journey from idea to patent. (Company white paper, February 2014)
“Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs”
Abstract: This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, the authors target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, the method can also be used to characterize the propagation delay across each fault-free interposer wire. (Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, March 2014)
“Local and Global Properties of a Lead-Free Solder”
Abstract: Elastic and viscous properties, including Young’s modulus, hardness, creep rate sensitivity, and fatigue resistance of Sn-1.2Ag-0.5Cu-0.05Ni lead-free solder, have been investigated. The properties of bulk specimens and in situ solder balls were compared. Experiments show good correlations of Young’s modulus and creep rate sensitivity between conventional measurements and nanoindentation results on bulk specimens. Further mechanical properties of the beach-ball microstructure in solder balls were characterized by nanoindentation. The load-partial unload technique was used to determine variation in mechanical properties with increasing depth of penetration into the intermetallic inclusions in the in situ solder. Fatigue resistances of the bulk specimens and solder balls were compared using the novel nanoimpact method. In comparison with bulk specimens, it was found that in situ solder has higher Young’s modulus, lower creep strain rate sensitivity and better fatigue resistance. The effects of soldering and the scale differences strongly affect the mechanical and fatigue properties of in situ solder. (Materials Science & Technology Conference, October 2012)
This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.