How do inspection discipline and sampling plans decide whether a shipment ships or gets torn apart?
Before going into PCB design, my employer was in the telecom business. I started out putting PCBs into antistatic bags, then into individual boxes with appropriate labels. A group of eight distinct boards was placed in a larger box to form a die group. The big box labeling reflected the part-dash number and revision for each board. This was called “final prep” and was the last step prior to shipping.
A structured design review process ensures alignment across teams.
One thing is certain about printed circuit board design: change is inevitable. The vernacular surrounding the art and science of PCB design gives credence to this statement. Upfront, it’s a schematic editor that leads to a layout editor. If you get far enough downstream, you’re working with a Gerber editor. Across the board, the notion of making changes is distilled into the process.
UCIe 3.0 is where bandwidth meets bravado.
In August, the Universal Chiplet Interconnect Express standard revision 3 was issued. This follows revision 2 by exactly a year. The first selling point of revision 3 is higher data rates, double that of the previous version. If that sounds like another standard, PCIe, then chalk it up to UCIe using PCIe as a template, along with the Compute Express Link (CXL), to build the UCIe ecosystem. It remains adaptable and scalable according to needs.
When passive heat management isn’t enough, fans or blowers are “cool” solutions.
It has been said that good things come in small packages. This is true of electronics up to a point. Chip companies compete for bragging rights over package size. Less is more. Increased density permits faster operation due to reduced lag in shorter traces. This trend extends beyond just chips; shrinking the entire product represents a significant “marketing breakthrough.”
Meanwhile, a compact board will have more wattage to dissipate per unit area. The power supplies are spread around the board with dedicated regulators assigned to each chip even when the voltage requirements are the same from one device to another.