The path to digitize a factory is both closer and cheaper than most engineers realize.
Reshoring has been a buzzword for a few years now. But when supply chains are undergoing dramatic disruption and inflation is raging worldwide, what is the reality?
According to research firm IDTechEx, it’s only a matter of time before an array of sensors and cobots spur far greater automation and flexibility. The firm recently published a white paper titled “Factory of the Future” that summarizes the expected advancements. Indeed, some of these changes are both relatively inexpensive and simple in scope yet open a realm of possibilities for greater process control.
IDTechEx senior technology analyst Matthew Dyson, Ph.D., who co-authored the paper, discussed the key trends in industrial manufacturing and the timeline for adoption with PCEA president Mike Buetow in late July. The following is lightly edited.
Mike Buetow:You just co-authored a white paper titled “Factory of the Future.” Lots of people, of course, are considering what that looks like. What spurred your interest?
Matthew Dyson: It’s the combination of technologies that we see being developed. The white paper is a compelling use case for them. It’s about how you can make manufacturing more efficient to address concerns like reshoring, inflation and so on.
Political and supply-chain issues could not slow printed circuit growth in 2021.
The author attended his first IPC meeting in 1966. At that time, the consensus was the world PCB output was $500 million. Some “knowledgeable” experts predicted PCB output would dwindle since semiconductors were rising rapidly and PCBs would not be needed. If that $500 million assessment was correct, in 55 years the PCB market grew 192 times, to $96 billion!
IPC-2152 is an important baseline for determining current carrying capacity, but further work must be done for individual applications.
In response to recent chatter about IPC-2152 in multiple online articles, I believed it necessary to reiterate the purpose behind the IPC design standard for sizing electrical traces.
IPC 1-10b is a task group of volunteers from several companies in the electronics industry. I was task group chairman from 1999 to 2016. We designed test boards and wrote IPC-2152, Standard for Determining Current-Carrying Capacity in Printed Board Design. The standard is intended to describe the test data used to define trace heating in a specific configuration through conductor sizing design charts. Testing was performed following IPC-TM-650, method 2.5.4.1A, “Conductor Temperature Rise Due to Current Changes in Conductors.” The design charts are only applicable to that configuration. Designs with different board sizes, thicknesses, and materials, including copper planes – when mounted by bolted fasteners or wedgelocks – have different trace temperatures for an applied current. People and corporations have to create their own charts if they want to have an accurate temperature for a given trace size and applied current. The information included in IPC-2152 provides that information. (Accurate temperatures can only occur from a design chart if that chart represents the specific technology.)
Summit Interconnect’s chief executive explains the PCB fabricator’s latest buy.
Summit Interconnect in May announced the acquisition of fellow printed circuit board fabricator Royal Circuit Solutions for an undisclosed sum.
But while the deal at first glance looks like the latest in a long string of capacity buys for the second-largest fabricator in North America, there is more to it than meets the eye.
For its part, Royal has engineering tools and staff that Summit can leverage to speed its own operations.
Royal also includes an electronics assembly operation, Aurora, CO-based Advanced Assembly. The EMS outfit’s quickturn production capabilities fit well with Summit’s commercial prototype programs. That the fab and assembly sides are integrated adds one more appealing facet to the acquisition.
Summit chief executive Shane Whiteside broke down the latest acquisition in an interview with Mike Buetow.
A new specification tackles the application and performance of organic solderability preservatives.
After many years of starts, stops and debate, an industry committee has finally developed a standard for organic solderability preservatives (OSPs). IPC-4555, Performance Specification for High Temperature Organic Solderability Preservatives (OSP) for Printed Boards, is out now, and it was a long time coming.
With the electronics industry fully entrenched in lead-free soldering, a standard for OSP is critical. There are more stringent requirements for solder joint reliability, resistance to corrosion, as well as additional requirements related to complex substrate designs.
The development and acceptance of IPC-4555 dispels the myth all OSPs are the same. With circuit boards fabricated around the globe, and small chemical firms attempting to introduce “new OSP processes,” buyers must be aware. Greater solderability requirements – measured as joint strength, paste spreadability and hole fill – and higher temperatures of lead-free soldering have greatly diminished use of conventional (standard substituted benzimidazole-based) OSPs. With the development of third- and fourth-generation organic solderability preservatives based on a novel aryl-phenylimidazole compound, however, OSP has regained its leadership role as a final finish, particularly in Asia and Europe. In addition, the technology shift to bare copper PWBs with selectively plated gold features requires OSPs that do not tarnish or deposit on the gold.
A single one can destroy a signal, but predictions with validated models can be made.
An ideal digital interconnect is a lossless transmission line with characteristic impedance and phase delay flat over the signal bandwidth and termination resistors equal to the characteristic impedance. In such interconnect, bits generated by a transmitter would flow seamlessly into the receiver with no limits on the bit rate. Such a utopian transmission line exists only in our imaginations and textbooks. The physics of our world prohibit it. One way to describe “what happens to the signal on the way to a receiver?” is to use the balance of power that can be written for the passive interconnect as follows:
This is frequency domain over the bandwidth of the signal.1 P_out is the power delivered to the receiver, and P_in is the power delivered by transmitter to the interconnect. All other terms in the balance of power equation describe the signal distortion. The formula above expresses all we need to know about the interconnects. (It should be “cast in granite.”). As they say, “a formula is worth a thousand words,” almost literally in this case. To understand it, imagine the interconnect system as a multiport with the transmitter at port 1, receiver at port 2 and multiple other ports for links coupled to the link connecting port 1 and 2 and terminations to real impedance (not necessarily identical at all ports) – something like this below, together with the definition of waves and scattering parameters (or S-parameters):
