Via temperature is determined by the temperature of the trace associated with the via, not the current itself.

Many designers and some EDA design tools place heavy emphasis on current density when sizing traces for a given current. Current density is current/unit area. Thus, it does make some intuitive sense that trace temperature might be proportional to current density: the higher the current, the higher the current density, and therefore the higher the temperature. But it is much more complicated. Following this design rule blindly may lead to significant design errors, especially when designing vias for allowable current. And a few examples will illustrate why.

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Novel coronavirus infection rates decreased over the past few weeks, and several countries are planning to ease stay-at-home restrictions that will permit some businesses to open.

The global economy is in a freefall, and small and large companies struggle to survive.

There is no specific treatment for coronavirus, and a vaccine is still months away. Virus testing for coronavirus is key, but it’s difficult to administer to millions of people. Polymerase chain reaction (PCR) is a technique used to amplify small segments of DNA; in layman’s terms, once you have your throat swabbed during a coronavirus test, the swab is ready for polymerase chain reaction testing. This test is not cheap, and PCR testing is not 100% accurate. A positive test result is 100% accurate, but 30% of the time you can receive a false negative result, meaning that people with an active Covid-19 infection still test negative for the disease.

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Unwanted capacitance hanging off signal traces can cause unwanted resonances and excessive attenuation.

Data rates for very high-speed data links keep climbing. PCIExpress Gen 4 is 16Gb/s, and Gen 5 is 32Gb/s. Data rates on links in high-speed routers and servers are as high as 56Gb/S. RF engineers would call all these microwave frequencies, even though they are “just” digital. It should come as no surprise that elements that did not matter at lower data rates can have significant effects at much higher data rates. Vias are one of these.

It has been shown many times that the vias used to connect signal pins to traces on innerlayers of PCBs are visible. It has also been shown that the effects of these vias can be ignored at the clock frequencies used until the advent of very high-speed differential signaling. Much to the dismay of design engineers, at very high data rates these vias often are the source of unexpected signal degradation, often to the point of failure. Here we show examples of this degradation and where it comes from, along with methods for minimizing this degradation.

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A test vehicle and qualification test for proving out process changes.

IPC J-STDF-001G states, “Unless otherwise specified by the User, the Manufacturer shall [N1D2D3] qualify soldering and/or cleaning processes that result in acceptable levels of flux and other residues.  Objective evidence shall [N1D2D3] be available for review.”1 (Ed.: N1D2D3 means no requirement has been established for Class 1, and the condition is a defect in Classes 2 and 3.)

In a qualified manufacturing process (QMP), manufacturing materials and processes used to produce electronics hardware are benchmarked and validated against electrical performance in hot/humid conditions.2 Characterizing chemical residues that exist on a manufactured assembly, and assessing the impact of those residues on electrical performance, has much to do with the end-use environment in which the hardware will operate. The other important factor is the circuit density and component types. Leadless and bottom-terminated components are more susceptible to residue challenges due to low standoff gaps, tight pitch, high solder mass, and blocked outgassing channels.

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Newfoundland may not appear to be a hotbed for PCB technology, but a team of startup engineers may change that.

There, on the Eastern edge of Canada, Liam Cadigan and Darryl Day, who grew up together, were working on degrees at Memorial University, where they met fellow engineering student Matt Noseworthy and budding computer scientist Nick Warren.

The group applied for the SpaceX Hyperloop competition, the Elon Musk brainchild that challenges teams of college students to design and build high-speed pods. The Canadian team didn’t win, but its second-place finish was good enough for Cadigan and Day to land jobs at another Musk startup, Neurolink.

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The novel coronavirus has spread to over 200 countries and claimed more than 150,000 lives. The virus emerged in China in December, and spread around the world.

European countries and the US report a significant amount of cases over the past several weeks. The total number throughout Europe is 1.1 million and the US reported 740,000 as of this writing.

The infection rate in Japan was relatively lower than North America and Europe last month, however, this changed over the past two weeks. The number of new cases surpassed ten thousand yesterday with over 200 deaths. New cases continue to increase, especially in the large cities of Tokyo and Osaka. The prime minister and prefectural governors issued emergency stay-at-home requests for at least one month hoping to reduce social contact. White collar workers are required to set up temporary offices in their residence and work from home, but manufacturing companies will suffer without any workers. Non-essential retail stores and restaurants are closed; grocery stores and pharmacies remain open. The Japanese economy will struggle during the second quarter.

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