The Taiwan Printed Circuit Association (TPCA) released December’s shipment data.

Despite channel changes, the major EDA vendors say user demand makes mainstream tools worth their continued support.

What is the future of the mainstream PCB CAD market? As printed circuit boards get denser, with ever more parts, models, nets, and materials to use and track, and organizations emphasize collaboration across locations and technical domains, can standard tools keep pace? Do the vendors have the pockets and desire to continue developing multiple solutions to common problems? Or will the market dissect into open-source and enterprise platforms with a vacancy in the middle?

In pursuit of an answer to these and other questions, PCD&F in January reached out by email and phone to the top vendors of ECAD tools. We heard back from all but one. Their perspectives are aggregated here, with some edits for length and clarity.

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Advanced high-Q RF components will play a critical role in larger goal of eliminating many of the latency issues of the past.

When WiFi 6 (IEEE 802.11ax) was introduced by the Wi-Fi Alliance, the standard was initially designed to operate within the licensed exempt bands between 1-6GHz. Then, on April 23, 2020, the Federal Communications Commission (FCC) announced it was adopting rules to open the 6GHz band (5.925–7.125GHz) for unlicensed use for WiFi 6 as well.

The highly anticipated move further boosts the expectations for increased speed well beyond the 30-40% already estimated compared to the previous IEEE 802.11ac standard. A significant boost in bandwidth is expected as well.

Assessing the cost vs. performance tradeoff.

In the evolution of silicon implementation, creative solutions to costly problems have become standard practice. One of these solutions is the use of a “chiplet.” A chiplet is precisely what it sounds like: a smaller version of a chip. This doesn’t mean it’s a miniature version. It means that only critical functions that derive significant benefits from a 5 or 7nm fabrication process are included on the chip. Other functions that will work well with 10nm or greater can then be fabricated with appropriate cost savings.

Chiplet technology creates a challenge, however. If all functions were included in the chip, the interfaces could more easily be measured and evaluated. These items now must be accounted for on a package or, more accurately, a system-in-package (SiP) (FIGURE 1). This places greater importance on the electrical characteristics of those interfaces and how that SiP implementation affects that behavior. Thus, there is a need to rapidly assess these issues with minimal effort for maximum results via virtual prototyping.

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