A summary of how to order layers to achieve target impedance values.

Printed circuit boards are becoming highly dense, hosting all kinds of high-speed interfaces. The bandwidth of the clock frequencies reaches hundreds of GHz, leading to complex issues related to EMI interference, crosstalk, reflections, jitter and losses.

These new challenges impact all processes involved in design, analysis, manufacturing and testing. Manufacturers employ advanced and complex technologies and methods to accommodate the higher density of functionalities packed into smaller components. To manage losses and achieve desired functionality at higher speeds, research into new materials is leading and revolutionizing this industry. The PCB is at the center of issues related to signal integrity, power integrity, electromagnetic interference, crosstalk, mechanical, thermal and more. It also plays an integral role in solutions for each of these challenges.

These issues begin at PCB stack-up design, since a well-designed stack-up forms the foundation of a strong and stable PCB. It acts as the fundamental backbone of the PCB design structure that impacts signal integrity, power distribution and signal impedance. A sound and properly designed stack-up minimizes the circuit’s vulnerability to external noise and helps improve the electromagnetic compatibility of the product (Figure 1).

Figure 1. The PCB is the center of a host of electrical, mechanical and thermal issues.

What follows is a summary of some key SI-related points in simple terms, without delving into deep mathematical calculations and complex theories. The stack-up is the arrangement of conductive and insulating layers within a PCB. The total number of layers in a stack-up is determined by the higher pin count ball grid array (BGA) components, complexity of the circuit, its placement and performance requirements. The order of these layers is very important and should be finalized carefully, taking into consideration manufacturability requirements and signal integrity (Figure 2).

Figure 2. Sample PCB stack-up configuration.

Regarding insulating layers, pay special attention to the properties of the dielectric material and its width. The type of material and its thickness significantly impact signal speed, impedance and losses. These materials play an important role in managing the mechanical and thermal stresses in the PCB, while the width of the dielectric material also contributes to the overall PCB width. Some conductive layers serve as power or ground planes (power/GND), while others function as dedicated signal layers. Designers use plane layers to establish power delivery networks (PDN) and carry high power signals from the power supply to their respective loads. In contrast, signal layers connect all manner of critical high-speed and other general inter-IC connections. Critical signals, which include high-speed signals on a PCB, require special attention and are highlighted in IC vendor datasheets.

Designers cannot route these signals on just any layer; they must meet specific timing and impedance-based requirements for the product to function correctly. For example, consider memory, the bread and butter of every design. DDR3 memory, for instance, operates as a high-speed interface that contains all types of signals, including data, strobes, address, command, control, status and clock signals. This interface can feature over 100 signals, each with specific timing and impedance requirements (Figures 3 and 4). The strobe and clock signals are differential in nature, while the remainder are single-ended, with different impedance requirements.

Figure 3. 50Ω single-ended signal routing in DDR3 interfaces.

Figure 4. 100Ω differential pair routing for DDR3 clock and strobe signals.

Regarding timing-related constraints, at a high level, data bits exist as bytes/lanes and each lane has its own differential strobe. In each lane, every data bit must maintain a timing relationship with its strobe and match the length of the strobes within a certain tolerance as provided in the datasheet. Additionally, all these data lanes must maintain a specific timing among themselves. All strobes in all lanes must maintain their timing with respect to the clock. The clock requires all address/command/control signals to match its length as well (Figure 5).

Figure 5. Serpentine routing for length-matching of DDR3 data, strobe and clock signals.

Design engineers mention these delay requirements in terms of time units, such as picoseconds or nanoseconds, while PCB layout designers prefer length-based constraints such as millimeters or mils. Converting time into distance depends on the signal’s speed on that particular layer, which relies on the properties of the dielectric material around the signal trace. These material properties also impact the trace impedance. All these factors are a part of PCB stack-up design, linking both speed and impedance closely to this design process. Let's explore how this connection works.

Stack-up design → Signal speeds

When electrical signals travel on the PCB traces, they generate waves of electromagnetic fields around them that travel along with the signals. These electromagnetic (EM) waves travel through the materials surrounding the PCB trace. In free space, EM waves propagate at the speed of light, which is 3x10^8m/s. In a PCB, however, there is no free space; instead, dielectric materials surround the signal traces. The speed of the EM fields in a PCB is affected by the effective relative permittivity (Er) value of the insulating material and is therefore equal to the speed of light in a vacuum, divided by the square root of the effective Er value of the insulating materials surrounding the transmission line; i.e.,

v = c / sqrt(Er)

In PCBs, FR-4 is the common dielectric material used, and its dielectric constant has a range of values from 3.9 to 4.7. To make it simple, take Er = 4 and put it in the above equation, which then reduces to

v = c / sqrt (4) = c / 2 = 1.5 x 10^8m/s = 150mm/ns ~ 6in/ns

In a PCB, the signal trace exists on an external layer (TOP/BOTTOM) or on an internal layer. When the signal trace resides on an internal layer, with a reference plane above and below it, as shown in Figure 6, the configuration is called a stripline configuration.

Figure 6. Offset stripline 1B1A configuration with signal trace between two reference planes.

In this configuration, the trace is completely surrounded by the dielectric material. Thus, the effective dielectric constant for this trace is equal to the Er value of the insulating material. For an Er value of 4, the speed of the signal on the internal layer will be approximately 6in/ns. The configuration in which a Cu trace is present on an external layer with a reference plane under it is called microstrip line configuration (Figure 7). In this configuration, the trace has dielectric material below it while air and solder mask typically sit above it. The Er value of the air/solder mask is less than that of FR-4. As a result, the effective Er value for the microstrip line drops below 4, leadings to higher signal speeds on external layers, meaning v > 6 in/ns. Signals always travel faster on external layers. Therefore, a signal routed on an external layer with a certain length experiences less delay compared to the same length of signal routed on the internal layer. Traces of the same length routed on different layers may have different delay times depending on the effective Er value for each respective layer.

Figure 7. Surface microstrip 1B configuration with a copper trace on the external layer.

From the SI timing point of view, this point is crucial when routing signals in an interface that needs to be length-matched. Route signals belonging to the same group on the same layer to control and easily match the delays. This practice explains why all signals of a DDR3 byte lane are routed on the same layer: it ensures they all maintain the same speed and, consequently, the same delay. Modern day layout tools have this capability built in. If the PCB stack-up is defined properly and all details of material properties and their widths provided, the tool calculates the signal speeds on every layer and can convert the delays into lengths (Figure 8).

Figure 8. Routing byte lane signals on the same layer.

Stack-up design → Trace impedance, Zo

Now it is time to discuss the relation of characteristic impedance, Zo, with the stack-up design. Closely review the Cu trace in the PCB: it makes a parallel plate capacitor with the reference plane below (Figures 9 and 10).

Figure 9. Copper trace and reference plane form a parallel plate capacitor.

Figure 10. Surface microstrip configuration (1B) affects impedance and signal integrity.

In a parallel plate capacitor, the two plates are separated from one another by air or by a dielectric material in the same way the trace is separated from the plane by an insulating material.

The capacitance of the capacitor is linked to the overlapping area of the plates (A), the distance between the two plates (d) and dielectric constant (Er) of the insulating material between the plates, through this formula

Capacitance = (A x Er) / d

For the capacitance of the PCB trace, the above formula can be written as

C = (w x Er) / h

The trace impedance, Zo, and its capacitance are related by the formula

Zo = sqrt (L/C)

It is evident and can be easily concluded that the trace impedance, Zo, is inversely related to its capacitance, C; i.e.,

Zo ⇐ ⇒ 1/C

This means that the factors that will increase the trace capacitance will in turn decrease its impedance, and vice versa. Keeping in view the formula C = (w x Er)/h, it can be concluded that:

• Increasing trace width, w, will increase trace capacitance but will decrease the trace impedance, Zo, and vice versa.
• Using insulating material with higher dielectric constant value (Er) will increase the trace capacitance, but will decrease its Zo and vice versa.
• Increasing dielectric material thickness (h) will decrease the trace capacitance, but will increase its impedance, Zo, and vice versa.

So, in a nutshell:

The trace impedance inversely relates to its width (w) and the dielectric constant value (Er) of the dielectric material, while it directly relates to the thickness of the dielectric material. These factors directly connect to the PCB stack-up. These parameters are tweaked to find suitable trace widths that achieve different target impedance values for all SE and diff-pairs. While making these calculations, ensure that the specified trace widths and spacing values are manufacturable and that selected materials are economical. Additionally, ensure impedance targets are met while keeping the thickness of the dielectric materials so that the overall PCB thickness is within allowable specs.

The stack-up design directly impacts signal speeds and trace impedances through the selected material properties in PCB layer construction. Engineers calculate and control parameters that affect multiple things at once. For example, changing the value of Er impacts both the trace impedance Zo and the signal speed. Sometimes, engineers alter material properties simply to achieve target impedance values, ignoring their impact on signal speeds. The result can be timing issues – product failure.

Akber Roy is chief executive of Rush PCB (rushpcb.com), a printed circuit design, fabrication and assembly company; This email address is being protected from spambots. You need JavaScript enabled to view it..

Artificial intelligence is superb at corralling volumes of data but still lacks the flexibility needed for many engineering tasks.

AI is transforming electronics design and manufacturing, making significant strides in everything from procurement to PCB design, and even defect detection. But while there’s a lot AI can do today, there’s still a whole lot it can’t (yet). Here’s what’s really happening on the ground according to experts in the field.

Celus’ André Reggiani says AI shines at retrieving datasheet information.

The easy consensus among those we spoke with is that AI automates the repetitive stuff. At Celus, André Reggiani, AI product manager, highlights that AI is really shining when it comes to “retrieving tons of information from datasheets” and helping engineers “find the right components for their circuits.” No more scouring datasheets, crossing fingers that you’re not missing something important. It’s like having an incredibly efficient assistant, but with fewer coffee breaks.

Zachary Feuerstein of Breadboard promotes AI’s cleanup capabilities.

Similarly, Zachary Feuerstein from Breadboard points to AI’s prowess in automating data extraction – think BoMs, RFQs, POs and supplier communications. “It can clean up unstructured data, extract part numbers and even handle back-and-forth emails with suppliers,” he says. This doesn’t just save time; it slashes the annoying admin work that no one signed up for in the first place.

AI can add structure to scattered information, Luminovo’s Timon Ruban says.

Timon Ruban, cofounder and managing director of Luminovo adds that AI is currently best used for “turning unstructured into structured data.” He explains: “Think ‘extracting a BoM from a PDF,’ ‘extracting the PCB specification from a PDF’ or ‘extracting technical parameters from a datasheet.’ AI is taking that chaotic, scattered information and turning it into something engineers can actually use.” This is a time-saver for engineers buried under mountains of unstructured data.

Problem Predictor

Forget waiting for things to break, AI’s got a crystal ball. According to Arch Systems cofounder and CEO Andrew Scheuermann, AI’s predictive powers are a game-changer. From anticipating when materials will run out to flagging potential downtime-causing machines, AI’s shifting the focus from reactive to proactive. This not only keeps things running smoothly, but it also keeps engineers ahead of the game, sparing them from panic mode.

It’s all about staying ahead of the curve. “AI’s now able to surface real-time, actionable guidance,” says Scheuermann. So, no more endlessly scrolling through dashboards. AI serves up the next best action, whether it’s pinpointing the nozzle causing scrap or identifying early signs of quality issues based on historical patterns.

AI’s Role in PLM – Streamlining Complexity

Duro’s Michael Corr believes AI’s strength is assessing bespoke datasets.

When I sat down with Michael Corr from Duro, we dove into why AI is such a strong fit for product lifecycle management (PLM). As he put it, “AI is great at handling bespoke datasets and making sense of them,” which is a step up from older machine learning tools that required everything to be perfectly formatted. This flexibility is why AI excels in the PLM space, where a mix of CAD content, manufacturing instructions, test data and more all come together. Instead of forcing all that info into a single format, AI can work with it as-is and still deliver meaningful insights.

Corr also highlighted how AI can cut down on redundancy across teams. “It’s easy for an engineer to recreate a part because they couldn’t find the original,” leading to duplicates and inefficiencies. AI can spot these issues by flagging identical or nearly identical parts, suggesting they be merged or removed. This streamlining of data helps strengthen the digital thread, making the entire process more accessible and collaborative. While we’re not there yet, Corr is excited about AI’s potential to not just organize data but also analyze changes over time and flag potential future issues before they arise.

Breaking barriers – literally. AI’s ability to break down language and cultural barriers is another unexpected perk. Scheuermann points out that AI tools are bridging global divides by translating across languages and dialects, allowing teams in different plants to communicate seamlessly. This means that once a solution is discovered in one factory, it can be applied to another without the hassle of language barriers. Talk about team spirit!

Alek Tyszka from Instrumental agrees, adding that AI can detect defects in real-time using computer vision. This means no more waiting to catch issues during the testing phase – AI spots them as they happen. But what’s next? Full integration from CAD to automated assembly and testing. The holy grail? A fully automated digital thread. But that’s still a few steps down the line.

The Current AI Struggle: Fully Autonomous Procurement

Now, let’s talk about the stuff AI still can’t do, no matter how many improvements we see. First up, Breadboard’s Feuerstein points to AI’s inability to act as a fully autonomous trading agent in electronics procurement. “AI still can’t dynamically buy components in real-time,” he explains. While it can forecast stock availability and help with price predictions, it’s not yet ready to pull the trigger on purchasing decisions without a human steering the ship.

Sergiy Nesterenko of Quilter.ai says AI falls short at managing design tradeoffs.

Sergiy Nesterenko from Quilter.ai also offers a sobering view of AI’s current limitations in PCB design. While AI is, to a degree, fantastic for automating routing and placement, getting a board ready in hours instead of days, he points out that the real challenge comes in designing something as complex as a motherboard. When it comes to “balancing signal integrity, power integrity, routing density and thermal relief,” AI isn’t quite at the stage where it can manage those trade-offs like an experienced human engineer. It’s like a juggler trying to keep too many balls in the air – something’s bound to fall.

Rui Calsaverini of Celus awaits AI’s improved interaction with engineers.

Rui Calsaverini, VP of R&D at Celus, echoes that sentiment: “Probabilistic systems like AI cannot generate an exact design on their own (yet),” he says. “The evolution in AI becomes more about how well it interacts with the engineer and the engineer’s intent.”

David Wiens says Siemens is focused on improving engineers’ productivity, not replacing them.

David Wiens of Siemens reinforces this design-focused view, noting that while AI excels in specific areas today, the leap to full design autonomy remains a major hurdle. “We’ve leveraged AI for things like natural language processing using large models, predictive analytics across the supply chain and rapid component selection based on datasheet information,” he explains.

These tools already help engineers identify part availability, streamline BoM creation and even predict optimal signal configurations much faster than traditional simulation. However, Wiens is realistic about what AI can’t yet do: generate high-complexity schematics and layouts. “Most of the tools you see today focus on simpler designs,” he notes, due to the lack of high-quality training data and the sheer complexity of real-world boards. “We’re exploring these technologies, but we’re focused on improving engineers’ productivity, not replacing them.”

Celus cofounder André Alcade adds engineers must still intercede.

André Alcade, Celus cofounder, adds: “These tools are producing higher-quality output over time, but even as the quality gets better, you can’t turn them into something for public use without an engineer’s guiding hand.”

From Design to Production – A Bridge Still Missing

At Celus, there’s a similar gripe about AI’s failure to bridge the gap between design and production in real-time. Alcade explains that while AI is excellent at interpreting block diagrams and datasheets, it still struggles to provide actionable insights that cut across both design and production. Imagine AI suggesting a design tweak based on real-world production data. Sounds like a dream, right? But we’re not there yet.

Scheuermann from Arch Systems agrees, emphasizing that unlocking real-time end-to-end intelligence is the big frontier for AI in electronics. “Once AI can bridge that gap, like surfacing how a layout decision impacts yield, we’ll see a massive leap forward,” he says. Right now, design and production still live in their own silos. AI can’t yet connect the dots in a way that can predict or fix issues on the fly.

Zuken’s Kyle Miller asserts AI can reshape PCB design.

Zuken’s Kyle Miller has laid out a compelling case for how AI is reshaping PCB design in ways that traditional rule-based automation never could. “It doesn’t do it like I would do it,” he wrote, citing a common frustration among engineers who feel that rigid automation systems don’t mirror their judgment or design style. His point is that past automation tools failed because they were brittle – too inflexible, too difficult to set up and too unaware of when breaking the rules was actually the best decision. AI, by contrast, “offers a fundamentally different approach, providing adaptive intelligence rather than rigid rule-following.”

Miller explains that modern AI systems can balance competing design priorities, customize to individual preferences and reuse design intelligence from past projects. He outlines key areas where AI is already helping – from intelligent constraint management during setup to adapting layouts based on previous successful designs. “By allowing the designer to interact with the PCB at a much higher level,” Miller argues, “it speeds up time to market but still keeps overall control with the designer.” Zuken’s own tools, he notes, already leverage AI for routing and decap placement, with more adaptive features planned for future releases.

The Road Ahead

While AI is undoubtedly making waves in electronics manufacturing, it’s clear that it’s not ready to take the reins. From making predictions before things go wrong to automating tedious tasks, it offers some serious time savings.

But there’s still a long road ahead, whether it’s perfecting procurement, mastering design trade-offs or integrating the entire design-to-production process, AI’s journey is only just beginning. As Nesterenko of Quilter.ai puts it, “AI’s real challenge is learning to make the same kind of tradeoffs as an experienced engineer.”

Stay tuned for more updates on how AI continues to shape the world of electronics. Who knows what it’ll do next?

Ryann Howard is managing editor of PCD&F/Circuits Assembly; This email address is being protected from spambots. You need JavaScript enabled to view it.. Prior to joining PCEA, she helped train the AI for a major US-based company.

A manufacturer’s perspective on determining parts layout.

A land pattern refers to the footprint or layout of surface-mount components on a printed circuit board (PCB). It includes the arrangement of pads, or lands, to which component leads or terminals will be soldered. An accurate land pattern is crucial for ensuring reliable solder joints, proper alignment of components and optimal electrical performance of the circuit. Most electronic component manufacturers provide detailed specifications and guidelines for creating land patterns specific to each component, which should be followed closely during PCB design.

Conventional wisdom regarding via count is wrong. Here’s the proof.

Conventional wisdom has suggested:

The cross-sectional area of a via should have at least the same cross-sectional area as the conductor or be larger than the conductor coming into it. If the via has less cross-sectional area than the conductor, then multiple vias can be used to maintain the same cross-sectional area as the conductor. (IPC-2152, page 26, Note 1)

In other words, if the conducting cross-sectional area of the trace (width * thickness) is n times greater than the conducting cross-sectional area of the via, then we need n vias. Almost the entire industry believed this, including those of us at UltraCAD, until Johannes Adam and I began publishing our research results (Note 2).