SMTAI Women’s Leadership Program highlights how technology shifts lead to greater opportunities for those with specialized skills.
The need to develop new technologies to meet the demands of artificial intelligence (AI) is increasingly urgent. The manufacturing of the necessary hardware at scale presents its own set of significant challenges, however, including highly skilled labor, specialized equipment requirements, automating complex tasks, supply chain disruptions and quality control issues. Given these manufacturing challenges, applying the principles of design for excellence (DfX) from the beginning of the design process is essential.
To illustrate, consider a specific example: the development of new interconnects, which are crucial for connecting the various components of an AI system. Interconnects are an example of the biggest bottleneck for AI performance. As electrical solutions near their physical limits, silicon photonics offer an opportunity to break through those limits by replacing traditional electrical interconnects with light. This permits significantly higher bandwidth, lower power consumption, reduced latency and improved thermal management, as photons inherently generate less heat and can transmit more data than electrons.
For advanced silicon photonics, the DfX challenges are particularly complex. The tight integration of optical and electronic components inside a single package, or even on a single chip, introduces a multitude of new variables for designers to consider. Design for manufacturing (DfM), for instance, must account for the precision needed to fabricate waveguides, modulators and photodetectors alongside traditional CMOS transistors, without disrupting the highly tuned CMOS manufacturing flow. This involves new processes, materials and devices, leading to challenges in design for test (DfT) as well, as traditional electrical tests may not be sufficient to verify both the optical and electrical performance, instead requiring the development of advanced photonics and electro-optic wafer-level testing. Furthermore, design for assembly (DfA) becomes more complicated due to the precise micron-scale fiber-to-chip coupling required for signal input and output – far more precise than electrical contacts – which can be sensitive to environmental factors and mechanical stress, driving the adoption of higher-accuracy assembly tools and precision manufacturing flows. These factors collectively increase the complexity of the entire design and manufacturing workflow.
Despite these challenges and progress toward solutions, technology is not static. The drive toward increasing bandwidth density and power efficiency drives new generations of technology, and with each new technology, we must address its unique DfX issues. For example, the industry is already moving beyond the limitations of traditional pluggable optical transceivers to more advanced architectures such as the 2-D co-packaged optics (CPO), 3-D CPO and 3-D photonics interposer to address the shoreline problem (the I/O interface being limited to the edge of the chip). In particular, sophisticated 3-D photonics interposer architectures such as Passage are emerging as a pivotal solution, offering an unprecedented ability to scale communication bandwidth for the most demanding AI workloads. This architectural shift, which spreads the I/O interfaces across the entire surface area of the chip, necessitates a further re-evaluation of DfX principles to ensure manufacturability, testability, reliability and yield as complex PICs and ASICs are combined more closely into a single package. The assembly flow and test points must be carefully designed upstream to optimize the yield of the final solution, and to enable high-throughput assembly and testability at every stage, such as wafer and package-level photonics testing via detachable fiber connectors (primary bottlenecks being fiber attach methods and optical testing from wafer to package level). These assembly and test complexities contribute to increasing cost pressure on the back end of semiconductor commercialization, namely, packaging assembly and test, as depicted in Figure 1, compared to the earlier dominance of front-end silicon costs.
Figure 1. Silicon photonics illustrative cost breakdown: silicon, packaging, assembly and test (graph for illustration purposes only). FCBGA: flip-chip ball-grid-array. CoWoS: Chip on wafer on substrate. SiPho: silicon photonics. (Source: Sandeep Sane, Peter Carson, Lightmatter; for illustration purpose only)
The changing DfX landscape, exemplified by this transition in networking technologies, necessitates highly specialized skillsets and adaptable engineers. Historically, women have faced barriers in traditional manufacturing roles (workplace conditions and culture, flexibility, work life balance); however, increasing demand for specialized skills during technology transitions such as the shift to silicon photonics leads to greater opportunities for women by rewarding deep technological and cross-functional engagement, as well as leveling the playing field in the absence of a sufficient existing talent pool. Work accommodations that emerged due to the Covid pandemic have established a new standard for flexible working hours and improved work-life balance, making this a perfect storm to rebalance the technology workforce from top to bottom for the benefit of women.
The Surface Mount Technology Association (SMTA) Women’s Leadership Program, to be held on October 20 in Rosemont, IL, is designed to address these very inflection points in technology and workforce development. Now in its 14th year at SMTA International (SMTAI), the program serves as a platform where technical innovation and leadership development intersect. Under this year’s theme, “Grab Your DFX Umbrella – It’s Pouring Possibilities,” the program explores real-world challenges and innovative solutions across electronics manufacturing. Through invited keynote presentations from women leaders in electronics and AI, attendees will gain perspectives on how to navigate emerging fields like silicon photonics, quantum computing, sustainability and advanced assembly. These sessions are complemented by roundtable discussions where participants can engage directly with industry experts and peers, tackling topics such as cleaning, harsh environments, PCB fabrication and assembly, repairability and test and failure analysis.
Just as DfX principles help us rethink manufacturability and reliability in next-generation technologies, the Women’s Leadership Program helps us rethink how to build a more diverse and inclusive industry that harnesses the full potential of its workforce. The challenges of tomorrow – whether silicon photonics interconnects for AI or entirely new architectures we have yet to imagine – will demand collaborative problem-solving and the widest possible range of perspectives.
By attending, you’ll not only expand your technical insight but also contribute to shaping a more inclusive future for engineering and manufacturing.
Learn more and register today: smtai.org/wlp.
Priyanka Dobriyal, Ph.D., is engineering operations director at Lightmatter and a member of the SMTA board of directors; This email address is being protected from spambots. You need JavaScript enabled to view it..
Figure 2. SMTAI WLP 2025 program.
