Features

A holistic view of 77GHz radar sensors as a PCBA build, considering fabrication, assembly and packaging materials.

The Society of Automotive Engineers (SAE) and US Department of Transportation classify levels of vehicle autonomy from 0 to 5. Level 0 incorporates no automation; levels 1-3 have varying degrees of partial assistance to the driver, where the automobile, for example, can control steering, acceleration and deceleration, and even interfere with the driver. Finally, in full autonomy, level 5, the car drives on its own and makes all decisions and reactions to its surroundings.1

The automotive market uses a combination of sensors to make these critical decisions. Radar designs are the fastest growing sensors in ADAS today, due to the longer-range capabilities and their resistance to all weather conditions.2 This research will focus on radar designs, specifically long-range 77GHz radar, to showcase how automotive materials are changing and, through the choice of alternatives to those conventionally used in the space, how product life and reliability can be enhanced.

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Recent salary survey results suggest newcomers may be entering the field.

Each year PCD&F surveys the PCB design community concerning issues surrounding their profession. For years, the feedback has had one connecting thread: Many PCB designers are experts with decades of experience. Their retirement has loomed large and has been widely anticipated, accompanied with concerns – and a little trepidation – about who will replace them. In conference classes and site visits in recent years, companies have discussed how they are working with educators at universities and local colleges to inform engineering students about industry opportunities. Recent survey results hint their efforts may be starting to pay off. And the time for boomer retirements is here.

PCD&F conducted its annual design engineers’ salary survey in early 2020, receiving 254 qualified responses from bare board designers, managers and design engineers. Data compiled included job titles and functions, ages, years of experience, education, location, types of projects, annual salaries and sales, job satisfaction and challenges, ECAD tools used, and years left in the field, among other data. While year-over-year changes are shown, they are for comparison only, and should not be assumed to be definitive.

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Via temperature is determined by the temperature of the trace associated with the via, not the current itself.

Many designers and some EDA design tools place heavy emphasis on current density when sizing traces for a given current. Current density is current/unit area. Thus, it does make some intuitive sense that trace temperature might be proportional to current density: the higher the current, the higher the current density, and therefore the higher the temperature. But it is much more complicated. Following this design rule blindly may lead to significant design errors, especially when designing vias for allowable current. And a few examples will illustrate why.

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Novel coronavirus infection rates decreased over the past few weeks, and several countries are planning to ease stay-at-home restrictions that will permit some businesses to open.

The global economy is in a freefall, and small and large companies struggle to survive.

There is no specific treatment for coronavirus, and a vaccine is still months away. Virus testing for coronavirus is key, but it’s difficult to administer to millions of people. Polymerase chain reaction (PCR) is a technique used to amplify small segments of DNA; in layman’s terms, once you have your throat swabbed during a coronavirus test, the swab is ready for polymerase chain reaction testing. This test is not cheap, and PCR testing is not 100% accurate. A positive test result is 100% accurate, but 30% of the time you can receive a false negative result, meaning that people with an active Covid-19 infection still test negative for the disease.

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Unwanted capacitance hanging off signal traces can cause unwanted resonances and excessive attenuation.

Data rates for very high-speed data links keep climbing. PCIExpress Gen 4 is 16Gb/s, and Gen 5 is 32Gb/s. Data rates on links in high-speed routers and servers are as high as 56Gb/S. RF engineers would call all these microwave frequencies, even though they are “just” digital. It should come as no surprise that elements that did not matter at lower data rates can have significant effects at much higher data rates. Vias are one of these.

It has been shown many times that the vias used to connect signal pins to traces on innerlayers of PCBs are visible. It has also been shown that the effects of these vias can be ignored at the clock frequencies used until the advent of very high-speed differential signaling. Much to the dismay of design engineers, at very high data rates these vias often are the source of unexpected signal degradation, often to the point of failure. Here we show examples of this degradation and where it comes from, along with methods for minimizing this degradation.

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A test vehicle and qualification test for proving out process changes.

IPC J-STDF-001G states, “Unless otherwise specified by the User, the Manufacturer shall [N1D2D3] qualify soldering and/or cleaning processes that result in acceptable levels of flux and other residues.  Objective evidence shall [N1D2D3] be available for review.”1 (Ed.: N1D2D3 means no requirement has been established for Class 1, and the condition is a defect in Classes 2 and 3.)

In a qualified manufacturing process (QMP), manufacturing materials and processes used to produce electronics hardware are benchmarked and validated against electrical performance in hot/humid conditions.2 Characterizing chemical residues that exist on a manufactured assembly, and assessing the impact of those residues on electrical performance, has much to do with the end-use environment in which the hardware will operate. The other important factor is the circuit density and component types. Leadless and bottom-terminated components are more susceptible to residue challenges due to low standoff gaps, tight pitch, high solder mass, and blocked outgassing channels.

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