Features

That’s one of the questions the new leadership at HDP plans to address in 2021.

This month Marshall Andrews stepped down as the longest-serving head of The High-Density Packaging (HDP) User Group. But as Larry Marcanti assumes the role of executive director of the decades-old electronics consortium, don’t expect big changes.

On Andrews’ 15-year watch, HDP’s membership increased by more than 30 companies, to reach more than 50 total. The ongoing project portfolio rose from five to an average of 25 member-driven activities.

Despite the Covid-19 lockdown, HDP is coming off one of its most successful years yet, having completed 13 projects. Marcanti and HDP facilitator John Davignon gave an update of the consortium’s latest work and future plans in an exclusive interview with PCD&F/CIRCUITS ASSEMBLY in December.

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A collaborative educational group formed in January and adapted virtually to bring the industry together.

A year ago, after IPC dissolved the Designers Council, its board members formed the Printed Circuit Engineering Association (PCEA) to continue their pursuit to collaborate, inspire, and educate the PCB design and engineering community.

The PCEA’s mission is to promote the printed circuit engineering profession by encouraging and facilitating the exchange of information and the integration of new design concepts through communications, seminars, and workshops. Its efforts are buttressed by a network of regional chapters and the support of sponsors, including several CAD companies and other firms.

The PCEA has a growing membership of more than 1,000 members, with existing chapters in Phoenix, Orange County (CA), San Diego, Silicon Valley, Ontario (Canada), Minneapolis-St. Paul, Monterrey (Mexico), Nogales (Mexico), Research Triangle Park, and Seattle. Chapters planned for the near future include Columbus-Cincinnati-Dayton; Grand Rapids, MI; Illinois-Wisconsin; New Hampshire-Massachusetts; Albuquerque; Houston; Dallas; and Austin. The PCEA hopes to open another Canadian chapter soon.

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Processes and tools for accurate lab analysis and defect detection.

Electronic sample preparation is a complex process that goes beyond merely lopping a piece off a PCB for inspection. This process involves several, exacting preparation stages.

The process designs each step to specifically adapt to the inspected device’s design, materials, and fabrication technology. Performing any of the preparation stages incorrectly can result in spurious features, artifacts and great potential for both Type I and Type II error.

The process starts with PCB manufacturers designing test coupon segments into each of their products. This function enables panel testing without wasting the actual production board. To confirm the lab has met product specifications, they separate the coupon from each panel.

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A look back at friends and colleagues who left us in 2020.

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Latest IPC-DPMX standard offers unique bidirectional data exchange between design houses and their manufacturing partners.

The authors of IPC-DPMX, previously known as IPC-2581, have come up with an innovative solution for addressing the needs of the industry for the latest version of the electronics data transfer standard. Developed for the industry by the industry, IPC-DPMX has many new enhancements. The just-released Revision C has been reviewed and unanimously approved by the PCB design, analysis and supply chain industry.

IPC-2581B introduced the concept of bidirectional data exchange between design houses and their manufacturing partners. It sought to eliminate the back-and-forth between partners at the very end of the design cycle for communicating and ensuring that critical net impedances were achievable. This communication was important earlier in the design cycle and impacted the layer stack-up, which is very hard to change at the end once design is complete and handed off. Although this innovation was unveiled almost seven years ago, it is still unmatched and unique within an open standard.

 

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As chiplet usage increases, chip-level concerns shift into the area of system-in-package implementation. Therefore, the system-in-package (SiP) must now accommodate electrical performance and cost considerations. A rapid prototyping tool flow that allows the engineering team to make quick assessments of these goals is essential.

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