Printed Circuit Design & Fab Online Magazine - Current Issue

Current Issue

Bill Hargin

The impedance implications of the trapezoidal trace.

Until recently I thought those who believed in rectangular traces were about as common as those who believe in square waves and a flat earth. Recently, though, I came to realize it’s not as clear as I thought, not only for newbies but in general. Over the past 25 years, I’ve acquired a good number of books on PCB design and signal integrity, and you wouldn’t know from reading most of the industry literature that traces were anything but rectangular. Interesting, right?

If you’ve read previous “Material Matters” columns, you may recognize the following cross-section from our Z-solver software. Among other things, it shows that the base of a trace, facing the core dielectric, is wider than the side of the trace that faces the prepreg. As such, the trace trapezoids face both up and down in a multilayer stackup. There’s no relationship to the layer number or whether the trace is on the top or bottom half of the board. For this reason, some including me – but not everyone – avoid using terms like “top” or “bottom” with regard to trapezoidal traces.

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Read more: Etch Effects Explained

Bill Hargin

Weight is still used as a determinant for copper thickness. Why?

Sometimes my columns tie to issues or stackups that appear in my inbox each week. I’m occasionally asked why 0.6 mils (15µm) is often used for the thickness of 0.5-oz. copper, rather than 0.7 mils (18µm), and similarly why 1.2 mils (30µm) is often used for 1-oz. copper instead of 1.4 mils (36µm). If you’re curious about the details, or if none of these numbers seems familiar, here’s a quick primer. The thickness parameter “t” in FIGURE 1 shows the thickness we’re interested in here.

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Read more: Actual Copper Thicknesses (As Opposed to What You’ve Assumed)

Bill Hargin

Trace separation; length parallelism; stackup: Does one stand out?

It’s been some time since I’ve seen an article on crosstalk, so I decided to take the opportunity to walk through the subject in a soup-to-nuts overview for those in the PCB design community who may be interested in why crosstalk-savvy PCB designers and hardware engineers use various design rules for controlling crosstalk. In the process of doing so, we’ll identify which design tweaks provide the most leverage for controlling far-end crosstalk.

Crosstalk is unwanted noise generated between signals. It occurs when two or more nets on a PCB are coupled to each other electromagnetically, (even though conductively they are not connected at all). Such coupling can arise any time two nets run next to each other for any significant length. When a signal is driven on one of the lines, the electric and magnetic fields it generates cause an unexpected signal to also appear on the nearby line, as shown in FIGURE 1.

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Read more: The No. 1 Weapon Against Crosstalk

Bill Hargin

Most boards will work just fine. But what if they don’t?

Over the past year, I’ve written a good bit about glass-weave skew (GWS) and next-generation loss requirements, using PCI Express guidelines as a means of tracking what higher frequencies do to eye patterns. This month, we’ll combine important elements of both these technology series, with just a bit of review in order to make this column one that can be read as-is.

The problem with human behavior is many of us wait for some sort of catastrophic event before we course-correct. When should we get serious about glass-weave skew, as opposed to ignoring it, while hoping it doesn’t turn around and bite us at some point in the field? (A near-worst-case scenario.)

When I was marketing signal-integrity software in the 1990s, many engineers would appear on my radar reactively, playing whack-a-mole after spinning multiple prototypes or field failures. Over time, the list of possible causes grew to include crosstalk, loss in all its forms, and eventually power integrity. I’ve noticed many of today’s hardware teams are sort of on cruise control relative to the “fiber-weave effect” as a design concern, so my objective here is to explore the concept of whether designers should worry about it proactively, given the potential impact of seemingly random field failure in production.

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