IEEE's annual conference of academic and research leaders reveals equipment and process advances.
The heat wave covering much of the Rocky Mountains in June was an apt metaphor for the annual IEEE Electronics Components and Technology Conference (ECTC) in Denver, where some 2,000 attendees heard the latest developments in advanced packaging. Thermal issues were as much a part of the proceedings indoors as out.
The conference in the Mile High City opened with a Heterogeneous Integration Roadmap (HIR) session. Presentations addressed the thermal challenges and specifically called out the needs for developments in metrology focused on thermal measurement. The conversation carried over into a parallel special session on metrology where participants from NIST, ASE, Intel, TSMC and KLA discussed challenges and opportunities in advancing metrology for next-generation microelectronics. The discussion culminated with a call to action to incorporate metrology challenges in every aspect of the HIR moving forward and potential for a future NIST workshop.
Read more: Hybrid Bonding and Thermal Concerns Heat Up Denver Discussions
Government-funded organization hopes to knock down barriers to commercialization.
The American Vacuum Society (AVS) held its annual conference in Portland, OR, with roughly 2,000 in attendance for the November meeting. The conference included many technical presentations by students, faculty and industry on cutting-edge issues associated with materials, processing and interfaces.
Among the highlights this year was a special session on the Chips Act. The session on the Chips and Science Act Implementation for Microelectronics (including workforce) was moderated by Dr. Alain Diebold, SUNY Polytechnic Institute, and Dr. Tina Kaarsberg, US Dept. of Energy Advanced Manufacturing Office.
The first invited talk was given by Dr. Jay Lewis, director, National Semiconductor Technology Center (NSTC). NSTC is a public/private consortium authorized and funded by the US government to serve as the focal point for research and engineering throughout the semiconductor ecosystem, advancing and enabling disruptive innovation to provide US leadership in the industries of the future. Dr. Lewis announced the incorporation of a new nonprofit entity, SemiUS, to operate the NSTC. SemiUS will work in partnership with the US Department of Commerce to develop and implement a wide variety of programs to fulfill the mission of the NSTC consortium. The focus is on building a strong semiconductor research and development ecosystem in the United States.
Read more: National Semi Consortium Starts with Next-Gen Workforce Focus
ECTC revealed the latest developments in 3-D hybrid bonding.
More than 50 presentations on hybrid bonding filled rooms to capacity at the IEEE Electronics Components and Technology Conference (ECTC) in Orlando, as did the Tuesday morning panel session. That panel discussion, on "Copper Hybrid Bond Interconnections for Chip-to-Wafer Applications," organized by Infinera and Qualcomm and moderated by TechSearch International, included perspectives from design and EDA (Synopsys) and research institute IMEC, users of hybrid bonding (AMD with production at TSMC and Intel with its internal development program), equipment makers Besi and EVG, and yield and reliability specialist PDF Solutions.
Synopsys pointed out the importance of design tools and IMEC described key drivers for 2.5-D and 3-D integration technologies such as increasing system complexity, increasing need for heterogeneous integration, increasing die-to-die interconnect data bandwidth (more interconnect channels and higher interconnect speeds per interconnect), reducing die-to-die interconnect energy with shorter distance interconnect, scaled, lower capacitance interconnects, and lower voltage. IMEC noted the issue is not the number of interconnects but rather the available (local) interconnect density enabled by interconnect pitch scaling. Many of today's hybrid bonding applications using die-to-wafer structures are focused on the high-performance space where the cost can be justified, including stacking SRAM cache and logic-on-logic, as introduced by AMD's products in desktop, servers, and AI/machine learning.
Read more: Advanced Packaging: The Hot Topic in the Florida Sun
Large crowds mulled the latest substrate trends and new developments in 3-D IC hybrid bonding.
The IEEE Electronics Components and Technology Conference (ECTC) returned to an in-person conference at the end of May with more than 1,500 attendees, domestic and international. Attendance in San Diego matched pre-pandemic numbers. While some presentations remained virtual, using video recording, many were onsite. A variety of electronics packaging topics were discussed. Judging by the crowded rooms, this year’s hot topic was 3-D IC hybrid bonding.
Advanced packaging. A pre-conference Heterogeneous Integration Roadmap workshop discussed trends in networking for the future and new developments in advanced packaging for high-performance computing and data centers. The workshop concluded with a panel of presenters discussing the latest trends in medical health and wearables.
Plenary sessions covered some of the latest topics. The MicroLED display session focused on high-volume manufacturing progress and challenges. In a session on the evolution of IC substrate technology, panelists from Intel, Amkor, Ajinomoto, AT&S and Atotech discussed the latest substrate trends.
IEEE's annual conference of academic and research leaders reveals equipment and process advances.
