PCD&F Magazine Issues

November 2010 Cover

FEATURES

DIFFERENTIAL PAIRS
Why You Should Care About Mode Conversion
Those familiar with designing high-speed single-ended interconnects don’t have a huge leap to design high-speed differential pairs. But a new problem can arise in differential pairs that has no comparable effect in single-ended interconnects, one that can completely swamp the differential signal at the receiver and can make the difference between a robust product and one that works with boards from some vendors but not others.
by Dr. Eric Bogatin

DfM
Best Practices for SMT Design
Fine-pitch devices and automation levels are resulting in greater board density. There are mechanical and logistical limits to how far these trends can go, however, and proper procedures will ensure manufacturability. 
by George Henning

RETROSPECTIVE
In Memoriam
A look back at friends and colleagues who left us in 2010. 
by Mike Buetow

SMTAI RECAP
Good Times in Orlando
In the technical sessions and on the show floor, SMTAI was a success. 
by Mike Buetow

 

FIRST PERSON

MONEY MATTERS

 

TECH TALK

November 2010 Cover

FEATURES

SIGNAL INTEGRITY
Generalized I/O Timing Analysis, Part 2
Timing analysis is a complex engineering process. It requires the engineer to deal with logic design, signal integrity simulations, PCB and chip design timing parameters, and generate length/delay constraints for chip/package/PCB designs. This, the second of a two-part series, looks at how timing and PCB trace lengths affect different real systems, and design tricks for tuning timing.
by Istvan Nagy

PCB WEST RECAP
Hot in the Valley
Something isn’t getting through, as signal integrity classes were packed even though most designers say they don’t perform the critical analysis. 
by Mike Buetow

COVER STORY
PCB Thermal Design Developments
Heat coupling increases as components and PCBs become smaller and more powerful. Designers must take remedial action to bring all components within their respective thermal specifications, but this step is becoming more challenging and constrained, even when preventative measures are taken early in the design process. New 3D thermal quantities can help address thermal problems as they arise. 
by Byron Blackmore, John Parry and Robin Bornoff

 

FIRST PERSON

  • Caveat Lector
    Tough choices call for single voice.
    Mike Buetow

MONEY MATTERS

  • ROI
    Our new stability.
    Peter Bigelow

 

TECH TALK

  • On the Forefront
    Flex’s new twists.
    E. Jan Vardaman

  • Signal Doctor
    Measuring differential pair loss.
    Dr. Eric Bogatin

  • Designer’s Notebook
    Landing spots.
    Tom Hausherr
  • Technical Abstracts
    In case you missed it.

October 2010 Cover

FEATURES

Generalized I/O Timing Analysis
SI/timing analysis can be performed heuristically, but there is a systematic approach as well. Timing analysis can be performed to create PCB layout design trace length constraints (pre-layout analysis), to determine the maximum data rate where the interface is still reliably operational (pre- or post-layout), and to verify an already routed board (post-layout analysis) would work reliably.
by Istvan Nagy

Team Design
No Reassembly Required
Introducing parallelism into the design process shortens, accelerates or recovers our schedules. The approaches to concurrent engineering. 
by Jamie Metcalfe

Perfect Paperwork
Best Practices for Preparing Documentation
Electronics assembly documentation includes files such as design schematics, assembly drawings, test procedures, BoMs and more. Problems or omissions in this documentation result in delays and, in extreme cases, may lead to product deficiencies and quality issues. How to ensure documentation for the EMS company is accurate. 
by George Henning

 

FIRST PERSON

  • Caveat Lector
    Still like Ike?
    Mike Buetow

  • Talking Heads
    Altium’s Alan Smith.
    Mike Buetow and Chelsey Drysdale

MONEY MATTERS

  • Global Sourcing
    What DoD cuts mean for the US PCB industry.
    Matthew Holzmann

  • ROI
    Do customers know what they want?
    Peter Bigelow

 

TECH TALK

  • Designer's Notebook
    Optimizing FPGA-to-board connectivity.
    Duane Benson

  • Final Finishes
    Giving you the ‘creep.’
    Lenora Toscano

  • Tech Tips
    Digital pre-distortion.
    ACI Technologies Inc.
  • Technical Abstracts
    In case you missed it.

September 2010 Cover-

FEATURES

Documentation
Automating the Documentation Process
“Documentation is much bigger than just design, fab and assembly,” experts say. A look at best-in-class processes that reduce the amount of time spent on drawings and notes by creating a “living” document.
by Mike Buetow

DfM
Best Practices for Double-Sided Mixed-Technology Boards
Plated through-hole assembly remains in use for some heavy power connectors, transformers and other devices where strong mechanical bonds are required. Reason: Heavy parts are prone to falling off during soldering.
by George Henning

 

FIRST PERSON

MONEY MATTERS

  • Global Sourcing
    Low cost: the death of innovation.
    Richard Platt

  • ROI
    Standard mistakes.
    Peter Bigelow

 

TECH TALK

July 2010 Cover-

FEATURES

Material Management
Benefits of Factory Software Interoperability
Manufacturers deploy various manufacturing systems that provide necessary controls, enable data collection, support cost-saving initiatives, provide a means for compliance, and help decrease time to market. Yet most remain as islands of information, and provide the value intrinsic within their own confined systems. Can overall equipment effectiveness be optimized by enhancing links between material flow, quality and surface mount technology programming, and monitoring data?  
by Jay Gorajia

 

FIRST PERSON

  • Caveat Lector
    Use proper protection.
    Mike Buetow

  • Database
    Not a standard opinion.
    Pete Waddell

MONEY MATTERS

  • ROI
    Certifiable.
    Peter Bigelow

  • Focus on Business
    Why one size doesn’t fit all.
    Susan Mucha

 

TECH TALK

  • Signal Doctor
    Ten electrical design lessons.
    Dr. Eric Bogatin

  • Designer's Notebook
    DfM, properly applied.
    Max Clark

  • Getting Lean
    When metrics fail.
    Tony Bellito

  • Technical Abstracts
    In case you missed it.

July 2010 Cover-

  • View the Digital Edition

     

FEATURES

COVER STORY
Practical Design of Differential Vias
A scalable, topology-based equivalent circuit model can accurately match via behavior to a bandwidth well above the application bandwidth, typically above 10 GHz. A look at a very simple way of modeling a differential via and translating its geometry into an equivalent circuit model. 
by Eric Bogatin, Bert Simonovich and Yazi Cao

DfF
Are Your PCB Data Unprepared?

It is great to have a fabricator that can provide its “secret sauce” to make the design work, but be ready to get locked into that supplier, because another fabricator’s recipe will be different. As a designer, is that a risk you want to take? 
by Jeff Champa

 

MONEY MATTERS

  • Global Sourcing
    China’s labor shortage.
    Tom Coghlan

  • ROI
    Hello? Anyone there?
    Peter Bigelow

 

TECH TALK

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