Capital Harness MPMT software application models harness designs against production capabilities to create structured bill-of-materials data. Is used to drive enterprise resource management systems. Helps identify what, where and how harnesses and their constituent sub-assemblies should be built. Identifies sub-assemblies common across different harness designs. Is part of Capital tool suite, an electrical system and wire harness design environment for the automotive, aerospace and defense industries.
Mentor Graphics, www.mentor.com
Impact backplane connectors are for data networking and telecommunications equipment. Contain a broad-edge coupled design that uses low impedance and localized ground return path in a differential pair array. Differential pairs are tightly coupled and surrounded by ground structures to isolate the pairs. Header construction offers air pockets selectively placed in the header floor to isolate signal pairs. Header signal pins are straight with no forms or offsets. Mating interface features a bifurcated beam with two points of contact with the second staggered 1mm behind the first. Offer two different hole sizes and tail lengths. Features include 25 Gb/s performance; 100 Ohm impedance; 0.46mm (0.018") PTH or 0.39mm (0.0154") PTH, and a robust daughtercard connector design.
TE Connectivity, www.te.com
N7000-3 polyimide laminate material complements N7000-3 prepreg. Has a UL 94V-1 designation, with no visible bromine. Is a high-Tg polyimide using toughened resin chemistry. For use in applications that require fine geometry, multilayer construction or extreme reliability.
Park Electrochemical Corp., www.parkelectro.com
LDI 5s Series pushes resolution below 10 µm, for IC packaging production and other fine feature products. Features rotor-based projection system for smooth, continuous scanning, proprietary spatial light modulation, twin-table stage, high bandwidth datapath for improved alignment overlay on individual panels in real time, unique autofocus, and more.
Micronic Mydata AB, www.micronic-mydata.com
RTL Power Model is designed to optimize a wide range of power-sensitive applications, such as ultra-low-power electronics. Predicts integrated circuit power behavior at the RTL level with consideration for how the design is physically implemented; helps enable chip power delivery network and IC package design decisions early in the design process; ensures chip power integrity sign-off for sub-28nm ICs.
Apache Design Inc., www.apache-da.com
Cadstar version 13.0 printed circuit board design software now has improved letter drill drawing creation; improved DXF import; improved routing, and an IDF interface.