NeoScale high-speed modular mezzanine connector now delivers faster data rates and improved performance. Offers clean signal integrity at data rates of 56Gbps NRZ. Composed of a vertical plug and vertical receptacle, with a patented modular triad wafer design for custom PCB routing in high-density applications. Patented PCB attachment method delivers robust solder joints. Is composed of three pins per differential pair—two signal pins and one shield pin. Each triad is a standalone, shielded, 56-Gbps-capable differential pair or an 8A power feed. Triads can be optimized for signals supporting high-speed 85 Ohm or 100 Ohm differential pairs, high-speed single-ended transmissions, low-speed single-ended or control signals, and power pins. Blind mateable with rugged triads for multiple connectors. Come in 12 to 42mm stack heights; circuit sizes of 8 to 300 triad wafers in 2-, 4-, 6-, 8- and 10-row configurations; and 85 or 100 Ohm impedance to provide optimal design flexibility. Customized versions available, such as 10 and 45mm stack heights.
Register now for PCB West, the Silicon Valley's largest trade show for the printed circuit industry, taking place Sept. 13-15 in Santa Clara: pcbwest.com
RO4730G3 UL 94 V-0 antenna-grade laminates meet performance requirements in active antenna arrays and small cells, notably in 4G base transceiver stations (BTS) and Internet of Things (IoT) applications as well as emerging 5G wireless systems. Flame-retardant (per UL 94V-0), thermoset laminates have dielectric constant (Dk) of 3.0, held to a tolerance of ±0.05 through the thickness (z axis) when measured at 10GHz. Are comprised of ceramic hydrocarbon materials with novel low-loss copper foil. Offer passive-intermodulation (PIM) performance better than -160 dBc typical, are 30% lighter than PTFE circuit materials, and feature a glass transition temperature (Tg) of better than +280°C for compatibility with automated assembly techniques. Z-axis coefficient of thermal expansion (CTE) of 30.3 ppm/°C from -55° to +288°C. Lead-free-process compatible. Dissipation factor of 0.0023 at 2.5GHz and 0.0029 at 10GHz.
Register now for PCB West, the Silicon Valley's largest trade show for the printed circuit industry, taking place Sept. 13-15 in Santa Clara: pcbwest.com
ACE Translator 3000 v 7.0 offers two-way translation between most common EDA, CAD, and 3D formats, in a single intuitive environment. Converts DXF, GDSII, Gerber, Postscript, PDF, ODB++, TIFF, BITMAP, STEP, STL, and more. Built-in viewer verifies translation results. Includes rulers, measurement tools, query, cell browser, hierarchy browser, HighLite broken polygons, plus new editing and repair features.
E3.series 2016 contains new usability and productivity features, plus automatic connect and auto-route functions said to significantly reduce design time and effort. Real-time, global design collaboration is possible with a true multi-user environment without sheet check-outs.
Tabular editing functionality has been extended to permit terminal strips for a whole project to be managed from within a table in a single window. Users may make changes to terminal connections directly from within the table. Placement column shows the current placement in panel layout using colors. Global search may be carried out to filter and search for terminal connections. Terminals, connectors and any devices can now be placed inside a block making blocks functional. Hierarchy within a block maximizes design reuse. Other features include automatic placement optimization when inserting, changing or deleting components; placing complete preconfigured terminal strips; and sorting terminal blocks according to customer criteria, as well as defining cabinet layout models for block components in the library. This enhances rack-based cabinet layout with predefined slots. Enhanced multi-user, real-time environment allows simultaneous work on one sheet. All objects can now be accessed online and concurrent design is achieved without needing to book out sheets.
Register now for PCB West, the Silicon Valley's largest trade show for the printed circuit industry, taking place Sept. 13-15 in Santa Clara: pcbwest.com
PXIe-5840 is a second-generation 1GHz bandwidth vector signal transceiver for RF design and test applications. Combines 6.5GHz RF vector signal generator, 6.5GHz vector signal analyzer, high-performance user-programmable FPGA, and high-speed serial and parallel digital interfaces into a two-slot module. Is suited for 802.11ac/ax device testing, mobile/Internet of Things device testing, 5G design and testing, RFIC testing, and radar prototyping. Measures 802.11ax error vector magnitude performance of -50dB. Has measurement speeds up to 10X faster than traditional instrumentation. Allows for up to 8 x 8 multiple input, multiple output configuration in an 18-slot chassis. User-programmable FPGA; can design with LabVIEW.
Pads PCB CAD platform features new analog/mixed-signal (AMS) and high-speed analysis tools for mixed-signal design, DDR implementation, and electrically correct design signoff.
Features:
Pads AMS Cloud, a cloud-based circuit exploration/simulation environment and user community, addresses analog/mixed signal simulation. Users from all levels of expertise can create and share analog, mixed-signal, and mixed-technology designs in an online, collaborative environment where designs and models can be published or downloaded. Circuit designs created in AMS Cloud can be transferred to the AMS Design Suite desktop environment, eliminating the need to manually recreate circuits to perform advanced analysis and drive the PCB design flow.
Pads AMS Design Suite, which allows design and simulation of analog/mixed-signal and digital in one environment. Within one schematic session, both analog circuit simulation leveraging VHDL-AMS, and topology exploration with the HyperLynx tool can be performed. Beyond common core AMS simulation analysis (DC Bias, time-domain, and frequency-domain simulations) additional extended analysis capabilities are included as standard, such as multi-run parametric sweeps, sensitivity, Monte Carlo, and Worst Case analysis to address specific engineering needs.
Pads HyperLynx DDR option, for integrated DDR simulation, which identifies and solves signal integrity (SI) and timing issues specific to DDRx designs.
Pads HyperLynx DRC tool, which accelerates electrical sign-off process by allowing electrical rules checks and identifying violations that will affect the design integrity and performance of the board. With predefined rules, reportedly quickly identifies issues such as traces crossing voids and traces changing reference planes on large designs. Integrated electrical DRC technology demonstrates PCB designs are electrically correct before hand-off to manufacturing. Key capabilities: Fast and easy time to results with a rules-based approach to identify non-CAD constraints; out-of-the-box checks for EMI, signal integrity and power integrity; easy identification of violations integrated with the PADS PCB product.
Each triad is a standalone, shielded, 56-Gbps-capable differential pair or an 8A power feed. Triads can be optimized for signals supporting high-speed 85 Ohm or 100 Ohm differential pairs, high-speed single-ended transmissions, low-speed single-ended or control signals, and power pins. Blind mateable with rugged triads for multiple connectors. Come in 12 to 42mm stack heights; circuit sizes of 8 to 300 triad wafers in 2-, 4-, 6-, 8- and 10-row configurations; and 85 or 100 Ohm impedance to provide optimal design flexibility. Customized versions available, such as 10 and 45mm stack heights.
