Blind, buried or smaller-sized holes can reduce plane voids and insertion loss.
High density interconnect technology can increase design density and reduce overall board size. It can also improve the signal and power integrity of a PCB. Here are two case studies that show how blind vias, buried vias and microvias can be used effectively.
Case 1: Improve power integrity by reducing voids in planes. High-power designs for high-speed digital signals require low impedance PCB power planes for proper operation. Therefore, solid planes for power and ground are always preferred. In many cases the power and ground planes under a BGA component have voids, as a result of through-hole vias. These voids have negative effects on power integrity, such as:
Increased plane inductance.
Increased plane resistance (as IR drop from power supplies to BGA pads).
Decreased plane capacitance.
Figure 1 shows how 8mil through-hole vias under a 0.8mm-pitch BGA have created voids in the three split power planes. The copper webs between the voids are just 3.5 mils wide. By replacing the through-hole vias with blind or microvias, the plane voids can be reduced (Figure 2).
Figure 1. Voids and split power planes under BGA component.
Figure 2. Voids eliminated with HDI technology.
Case 2: Improve signal integrity by eliminating via stubs. At speeds of 5Gbps or 2.5GHz and faster, via stubs begin to have a noticeable impact on the insertion and return loss of a PCB. Through-hole via stubs can be removed mechanically in some applications, but in the case of PTH high-speed connectors, such as backplane connectors, pins cannot be back-drilled. One solution is to use surface-mount high-speed connectors and blind vias (Figure 3).
Figure 3. Through-hole via stub, before and after.
Figure 4 shows two via stubs in both ends of a through-hole via for layer exchange of striplines. Buried vias, then, can be employed to eliminate the stubs.
Figure 4. Through-hole via stub, before and after.
In these cases, the use of blind vias and buried vias completely eliminates the through-hole via stub, improving the signal integrity of the PCB.
These are just two situations where HDI technology enables a layout designer to produce better quality PCBs. With recent advancements in PCB manufacturing capabilities, look for many more case studies to come.
With few exceptions, large vias are not ideal for ground pads.
I recently received a question on Twitter, asking: “What is your opinion on the ‘one big plated drill in QFN ground pad’ pattern?”
I answered back in 140 characters or less: “Bad for machine assembly, okay for hand assembly.” That’s definitely a true statement, but it’s worthy of a bit more explanation. Figure 1 shows the side opposite of where the QFNs are mounted. The two big openings in the square gold pads are the big vias (plated drill). This is often done when hand soldering QFNs. First, on the component side, solder the little pins on the outside edge of the QFN. Then turn the board over. Stick your soldering iron and solder into the big opening to solder the pad down.
Generally, there wouldn’t be any reason to do this with machine assembly, as we do here in our plant. The proper thermal approach is to put a number of small capped vias in the pad area. The solder paste layer (AKA stencil layer) in the CAD library needs to be segmented to allow for 50 – 75% paste coverage. Thus, we would never recommend using big vias, like those in Figure 1, for machine assembly.
However, I can envision some situations that might call for this. First, when hand soldering, as I mentioned above. Next, there may be some very specific need to expose a lot of the pad to open air for cooling. This is not the best way to get cooling, but it may work in some special instances. Third, perhaps access is needed to the pad as a test point and there’s not enough room to get access any other way.
None of those three steps would be taken in a production environment, but in a prototype world sometimes things happen differently.
SMT? Or not? Sometimes parts labeled as surface mount aren’t quite ready for prime time. In this case, I’m not referring to components that aren’t up to thermal par. Instead, I’m talking about components that can take the heat, but aren’t set up to be machine assembled.
Surface mount machines need a flat surface to pick on. The machines use small vacuum nozzles that need to seat on that flat spot. Chips, of course, are flat on top, as are most other components. Connectors, however, are often not flat on top. That doesn’t leave any place for the pick-and-place machine to pick.
Generally, manufacturers will place a small tab of Kapton tape or a small snap-in plastic pad on top of the connector, giving the machine a surface to work with (Figure 2). Once the board has been fully assembled, the tape or plastic pad is simply removed.
Every now and then, we’ll see connectors come in without that flat pick-and-place surface (Figure 3). That means the machine can’t place it, so it will have to be placed by hand. If there’s a choice between a part with the tape and one without, pick the one with the tape. No offense intended to all of you humans, but machine assembly is way better than human assembly.
Keep power and ground impedance as close as possible.
Capacitors are amazing little devices. They keep our camera flashes flashing, our stun guns stunning, our electric motors starting, and our stereos thumping. And on a PCB, they keep our ones 1-ing and our zeros 0-ing. Capacitors form the backbone of PCB power distribution networks (PDNs), and high-speed digital devices wouldn’t work without them. Not only do capacitors provide high-frequency energy to ICs, but they also provide AC return current paths for the signals travelling between them. But they can be rendered much less useful – and sometimes useless – if not properly mounted to the board.
You’ve probably seen the design guidelines that show capacitor mountings as good, better and best. “Don’t connect your capacitors with long traces.” Well, how long is too long? And how much better is “better?” The answers vary somewhat depending on the specific PCB, of course, but I set out to analyze some of the more common situations and actually quantify them.
I created a test board (Figure 1) that was 10" by 10" and connected an array of 100 0402 capacitors, and analyzed the properties of different mountings.
The type 0402 is one of the more common high-frequency capacitor sizes, and I used 0.22µF capacitors. A more common value might be 0.1µF, but it is generally a good idea to use the largest capacitance available for a given capacitor body size. The reason is that the inductance of the mounted capacitor is the limiting factor for its performance, and capacitors with smaller bodies have lower inductance. So, for a given body size, or inductance, the greatest capacitance will produce the lowest impedance over the widest frequency range possible. If there were such a thing as 1000µF 0402 capacitors, those would be the caps to use!
The main goal of PDN design is to minimize the impedance between power and ground, across a range of frequencies. In the high-frequency world, the greater the capacitance between power and ground, the lower the impedance. The lower the inductance between power and ground, the lower the impedance. Since 0402 caps are small, they have a low inductance. However, their small size also limits the amount of capacitance that can be crammed inside them, so you need to use a large number of them in parallel to get a large capacitance.
To analyze the impedance of our network of capacitors, we can use an analysis tool to generate an impedance plot, or Z-parameter, of our power distribution network. I started by analyzing the impedance of the test board with the caps connected to the power and ground vias by 5 mil traces that were 50 mils long. This is the top capacitor mounting configuration shown in Figure 1. The impedance plot is shown in blue in Figure 2.
In an attempt to reduce the inductance of that trace connection, I widened those traces from 5 mils to 20 mils. The resulting impedance plot is shown in pink in Figure 2. Basically, there was only marginal improvement. The main problem with that configuration is the distance between the vias, as it creates a large loop area for the connection between power and ground. So for my next configuration, I moved the vias as close as possible, using a via-in-pad configuration. The resulting change is shown in the red impedance plot in Figure 2, which is nearly an order of magnitude lower impedance above 10MHz.
It is important to note that this analysis was done using what is called lumped analysis. This kind of analysis can be performed with a spreadsheet or other simple PI tool, and it basically lumps all the capacitors and board capacitance into a single node. It is a good planning tool, but its limitations should be understood. A PI tool that can use actual board geometries for the traces, vias and planes connected to the capacitor will give valuable data on the mounted performance of a capacitor. This is what was used in the lumped analysis. However, beyond the mounted parasitics are other parasitics associated with the capacitor(s) connection to the IC. To include these effects, perform a distributed analysis, which looks at the PDN impedance at the IC location. In Figure 2, the orange waveform is the result of a distributed analysis with the via-in-pad capacitors. The results look much worse than the lumped results (in red).
How can we improve these results? As noted, mounting is only part of the capacitor’s effect on the PDN from the standpoint of the IC. To minimize the PDN impedance, the entire loop area, and hence inductance, between the capacitor and IC must be minimized. In this case, the capacitors were connected to the planes on Layer 3 and Layer 6 of the stackup, which are spaced very far apart (in this case 36 mils), as shown in Figure 1. This is actually a very common practice in 6-layer board stackups, and as can be seen, the results are very poor. If the capacitor were instead connected to Layer 6 and Layer 7, which are only 3 mils apart, the results are improved dramatically (Figure 3, green plot). Although that change results in longer via connections to the planes (compared to the orange plot), the reduced plane separation creates a much lower impedance path to the IC. If the capacitor is instead connected to the planes on Layers 2 and 3, the via connection distances are made shorter, resulting in a marginal improvement (the light blue plot). Here you can see the importance of close power/ground spacing in the stackup. Even further improvements can be made by connecting all the power/ground planes in parallel (shown in yellow).
Can further improvements be made? Employing some PI-specific technologies, which usually incur an additional cost, can also help. For instance, using reverse aspect ratio capacitors, such as 0204s, can make the mounting inductance even smaller (shown in gray). Use of dedicated board capacitance materials that are very thin (>1 mil) with very high dielectric constants can also help by providing additional decoupling capacitance, as well as shrinking the loop inductances. For my sample board, I replaced the 3-mil dielectrics with 0.3-mil dielectrics with a Dk of 16 and saw substantial improvement in the PDN impedance (shown in white).
In summary, maximizing capacitor effectiveness is all about keeping power and ground as close as possible. Vias connecting capacitors should be as close as possible, and connected to a plane pair that is as close as possible. Doing these simple things in your PCB design will keep the capacitors happy and productive.