Printed Circuit Design & Fab Online Magazine

Designer’s Notebook

John Burkhert, Jr. As PCB designs grow more complex, partitioning and teamwork become part of the layout strategy.

Printed circuit board design grows in complexity with each passing year. Many protocols must be implemented. An ASIC (application-specific integrated circuit) or an FPGA (field-programmable gate array) may be the center of attention, but there will likely be a memory bus along with other architectures, such as ethernet or USB, to move data around. Interacting with the world around us requires some sort of sensor to read the room, while other circuits are used to feed this processed data back to the user.

Read more: Splitting a PCB for Concurrent Design

John Burkhert, Jr. How do inspection discipline and sampling plans decide whether a shipment ships or gets torn apart?

Before going into PCB design, my employer was in the telecom business. I started out putting PCBs into antistatic bags, then into individual boxes with appropriate labels. A group of eight distinct boards was placed in a larger box to form a die group. The big box labeling reflected the part-dash number and revision for each board. This was called “final prep” and was the last step prior to shipping.

Read more: Inspecting Printed Circuit Boards and Assemblies

John Burkhert, Jr. A structured design review process ensures alignment across teams.

One thing is certain about printed circuit board design: change is inevitable. The vernacular surrounding the art and science of PCB design gives credence to this statement. Upfront, it’s a schematic editor that leads to a layout editor. If you get far enough downstream, you’re working with a Gerber editor. Across the board, the notion of making changes is distilled into the process.

Read more: Reviewing the PCB Design Review Process

John Burkhert, Jr. UCIe 3.0 is where bandwidth meets bravado.

In August, the Universal Chiplet Interconnect Express standard revision 3 was issued. This follows revision 2 by exactly a year. The first selling point of revision 3 is higher data rates, double that of the previous version. If that sounds like another standard, PCIe, then chalk it up to UCIe using PCIe as a template, along with the Compute Express Link (CXL), to build the UCIe ecosystem. It remains adaptable and scalable according to needs.

Read more: Interconnect Technology for Chiplets