Printed Circuit Design & Fab Online Magazine - Current Issue

Designer’s Notebook

John Burkhert

Determining your optimum geometry, plus two methods for providing data to the fabricator.

Controlling impedance (resistance) is almost a given with today’s technology. One day we are adding a wireless option to a common object and calling it the Internet of Things. The next day we’re simply keeping up with the competition on processing the code. The trend is toward a greater percentage of the connections falling under the domain of impedance control.

Controlled impedance has two main branches: Single-ended transmission lines are the backbone of RF technology, while differential pairs do the heavy lifting for digital circuits. We’ll start with the single-ended lines. They have a start and an end point. The signal is sent one way on the transmission line, and the circuit is completed over the adjacent ground plane.

The main factor influencing impedance is the width of the trace relative to the thickness of the dielectric material between the trace and the ground plane – or planes – used as a reference. What is a reference? It is usually a metal plane with zero volts – “ground” but can have a few volts of its own, either positive or negative relative to what’s happening on the trace itself.

Read more: How to Specify Impedance on a PCB

John Burkhert

Keeping some margin on the table increases the chances of immediate success and leaves a little bit for later.

There are many more ways to constrain a PCB layout than when I started my journey as a semi-intelligent designer. Guardrails were put in place to smooth transition into fabrication once the layout is completed. The other thrust of newer rules concerns the shrinking timing budget of our digital interfaces, particularly the memory banks.

We have so many aspects we can control that it can be tempting to disable or ignore some of them. That is a completely rational choice to make. New features take time to learn and implement. It may not be so easy to get everyone on board for a new feature or a whole new iteration of the software.

I remember getting buy-in to move up to a different whole number revision of the ECAD tools by reminding the team we didn’t have to use any of the new features and could go on using the tool exactly as before. It’s easy to get comfortable with what you have if that gets the job done to everyone’s satisfaction.

What we do is observed by many of the people around us. A narrow focus ends with the various EEs and your management team. Truly satisfying everyone takes a much wider view of the situation. Who is watching? Practically the whole company – and then some.

Read more: Reasons to Go Beyond the PCB Constraints

John Burkhert

Component manufacturers continue to seek breakthroughs, adding functions and reducing size, while fan-out is left to the designer.

While the printed circuit board is composed of sheets of dielectric and conductor layers, it’s the vias that really bring a circuit to life and keep it going. Permitting signals to pass from one layer to another makes this a 3-D puzzle that can scale to a staggering number of layers.

You don’t have to go back many decades to find a time when we called them printed wiring boards. (Officially, the standards still do.) Components were mounted to what looked like a pegboard: rows of evenly spaced holes where the leads of the part extended through two or more of the holes. You just added wire. As far as routing consistency, every board was a one-off, built up one wire at a time.

Give credit to government agencies for driving PCB technology toward higher reliability. Along the way, the “industrial complex” responded with the following electronics innovations:

Individual transistors advanced to integrated circuits using dual-inline package technology.
Axial- and radial-leaded passive through-hole components gave way to surface mount types with and without leads.
Quad flat packages (QFP) and similar devices came along with a full perimeter of signal pins, plus a ground slug taking the central area inside the single ring of pins.
Ball grid array (BGA) packages now featured a partial or full field of pins.

Read more: Selecting the Appropriate Through-Via Technology for a PCB Project

John Burkhert

Shortening and folding traces takes creativity and persistence, as long as the timing budget is met.

Printed circuit boards are becoming more complex, with high-speed interfaces more common. Whether it is a PCIe, Ethernet, USB or memory of some kind, clock nets proliferate across the board. Those clocks have kindred spirits in nets that want to hit the receiver in conjunction with the ticking clock.

Crucial parameters of a group of traces include the target length or maximum. Less is more. Most other signals on the board will switch periodically. Meanwhile, the clock switches all the time. The clock uses the same voltage, but the constant stream of “10101010101…” creates more energy fields than a seemingly random sequence of ones and zeros. These constantly shifting reactive clock net fields are the reason we shield the clock, giving it space to do its thing.

Shorter traces equal lower electromagnetic emissions. Shorter clocks have comparatively lower emissions and are less lossy. This gives rise to the use of available length matching tolerance to minimize the length of the clock, starting with finding the longest member of the group. Look at that net; locate any extra bends or places where it can be shortened.

Read more: Length Matching Routing for PCB Busses