Why a 3-N-3 stackup is the sweet spot.

The leading cause of HDI requirements comes from the chip vendors. The original ball grid array packages supported regular vias. Little by little, the pins got cozier. The 1.27mm pitch became 1mm, then 0.8 down to 0.65mm center-to-center. This was the final node where plated through-hole (PTH) vias was an option.

The next step down is 0.5mm class BGAs. We can still use a through-via embedded in the solder pad, but there are two issues. One, the via must be filled and capped to produce a flat surface that doesn’t permit solder to drain away during reflow (FIGURE 1). The other is that the typical “8/18” via has a finished hole size of 0.2mm and a capture pad of 0.45mm. On a 0.5mm pitch device, that leaves 50µm for a trace and an airgap on either side of the trace. That’s not practical.

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