Simple constraint and design rule checks can set the maximum stub length.

It’s no secret that placing passive devices in the proper location, whether nearer to the source/driver or the receiver/load pins, is the difference between poor signal integrity and optimal signal integrity. Often this can be impacted by a breakdown in communications between circuit designers and PCB designers.

Typically, the circuit designer has the background information such as distance and constraints, and can determine best the placement of these devices. However, this information may not be provided to the PCB designer during the initial placement phase, leaving them in the dark.

The following are tips on how to achieve the correct placement of passive devices, including a look at the maximum stub lengths option that helps avoid improper placement issues.

Tips for proper placement of passive devices.

1) Perform a manual check of vendor specifications for component placement and topologies.

• The circuit designer should share the vendor specifications of the devices with the PCB designer.
• The PCB designer carries out the checks per the specifications that apply to physical layout.

2) Work with the circuit designer to gain a comprehensive understanding of the vendor specifications by asking questions like:

• Are there length- or delay-based requirements to control skew?
• Are there critical placement requirements for termination devices?
• Are there required routing topologies that must be followed to maintain proper stub lengths, i.e., applying daisy chain or star topologies?

3) When the design is complete, work together on the circuit simulation to understand where errors may be and put together a comprehensive design rework plan to eliminate further cycles of simulation and rework.

There is another way to tackle this problem that eliminates some issues related to critical placement of termination devices. You can use a simple constraint and design rule check. The circuit designer can set constraints that the PCB designer can then apply to the design using CAD software. The rule known as “maximum stub length” can be further controlled using a graphical topology editor.

What is maximum stub length? When I instruct PCB designers in high-speed constraint management and routing classes, I always ask this question: “What is maximum stub length?”

The most common answer is: “It relates to the routed trace stub from an SMD pin to a via.”

Depending on the PCB design software being used, the answer is not completely wrong. In all honesty, I don’t expect PCB designers to know the answer. In fact, many PCB designers agree that it is the circuit designer’s job to know this and to communicate the rules to them.

Maximum stub length is the length at which the trace will start to behave as a transmission line and at which it becomes capable of causing signal reflections. This behavior occurs when routed signals are branched off using what PCB designers refer to as tee-routing, or routed lengths to termination devices are too long.

The premise is that physical length must match a timing requirement set according to the manufacturer’s measured results of the ICs on a test fixture.

Many other forces and factors are at work here, but the point remains the same: when routing a daisy chain topology, PCB designers try very hard to avoid tee-routing patterns. While this is a good rule of thumb, there may be a little more leeway than one would expect when observing maximum stub length values.

Using the maximum stub length constraint. While it’s not the PCB designer’s role to challenge the manufacturer’s specification, it is ordinarily the circuit designer’s responsibility to provide this information in the form of a constraint or rule (not just as text notes). This small added step provides big benefits with an additional design rule check to seek out violations of the maximum stub length rule, and at the same time, it can also be used to help with the placement of passive devices used for termination.

The simple topology in Figure 1 shows an Enet with the driver pin passing through a resistor and then a transmission line before terminating at a receiver pin. Using a constraint browser and topology editor for schematic capture in combination with signal integrity simulation, circuit designers can graphically create and simulate the effects of stub length using pin symbols, components and transmission lines. No more handwritten notes, hand routing, clock signals, etc.

When the circuit designer provides the stub length values, the PCB designer has rules to guide the placement of the devices. The PCB designer places devices on the PCB layout and sees a dynamic fence appear along with constraint indicators as guides (Figure 2).

By constraining stub lengths through passive component placement using CAD software, designers can overcome challenges associated with the improper placement of passive devices used for Enet signal termination.

Andy Buja is a senior applications engineer for CADStar and CR-5000 at Zuken; This email address is being protected from spambots. You need JavaScript enabled to view it..

Multek in July announced it would open a major tech center in the Silicon Valley, performing critical research on everything from new materials and manufacturing processes to signal integrity. Multek president Franck Lize and CTO Dr. Bill Beckenbaugh discussed the Innovation Technology Center with PCD&F editor in chief Mike Buetow via phone.

MB: Has the ITC been in the works internally for some time?
FL: So the new center is very interesting. We spent the past four months with customers to understand what their requirements were for the next-generation products. With the telecom market, with the 4G and 5G, and even the consumer business with flexible products like wearables and the flexible phones that we hear about in the news, there’s a change (coming) in the PCB industry because there are different requirements for those PCBs.

Our customers need many more solutions now than ever in the past 20 years. Multek wants to be a pioneer here. The ITC is part of the solution that Multek is putting together.

MB: Is it a standalone entity?
FL: It’s part of a full system. We are co-located next to the big NPI center that Flextronics has in the Bay Area. We needed a place for knowledge and engineering, and we wanted to be in the best location in the world for electronics. But the ITC is  much more than that. We are leveraging on our network of field applications engineers, which we have all over the world. Thanks to this extended network, our customers have direct access to this great capital of PCB and flexible circuit knowledge, no matter where in the world they are. It fits into the full Multek solution. Whether it’s a field application engineer or our top engineers in the Silicon Valley, we are working to provide early engagement for new materials, signal integrity issues, and new flexible designs. For any new challenges that our customers have, Multek helps them make the bridge between concept and actual manufacturing.

MB: We are seeing companies such as Agilent and IBM change their paradigms so that their design kickoff meetings involve everyone from the SI engineer to the hardware engineer, the firmware guy, the fabricator and the assembly process engineer. The DfM rules are hard-coded at that time, so that there are no changes down the line. What are you seeing insofar as this, and did it play into your decision about the ITC?
BB: This is the trend we are seeing over the past several years, and it’s why we wanted to move past our internal paradigm and turn it around so that the requirements and cost of the functions are designed in early, because if we don’t participate in it, we won’t be able to help the customer do a better job, but also because they might be doing something using an older technology than they need to, one that might cost them money or be less efficient.

We wanted to make it customer-focused and not limited, an open-ended ability to create a team and bring the right people with the right answers to the right problem set. It also helps us define our future capacity and technology requirements better.

MB: To what degree will ITC be involved in blue sky research outside of what’s directly needed by customers?
BB: Blue sky for us is defined for something that’s been coming, but traditionally we have put it in terms of the optimum solution for copper-based interconnects. At some point we will move to other ways to move to signal propagation. The future will be very different.

This industry has only gone through two or three revolutions in the past 25 years. We feel the next one is coming in the next few years. I don’t want to give too much about that because of the proprietary nature of it, but it is something we are working on.

MB: Bill, what are you seeing in terms of 3D packaging?
BB: Being located with the Product Innovation Center, we are able to provide the interconnect part to accelerate our Flextronics corporate roadmap, and provide a Multek interconnect solution for MEMs packaging. We are in mass production on product with package-driven interconnect pitches and component densities and assembly requirements. We see sensor integration and integration of MEMS devices is a key driver of the next generation of interconnect solutions. I’ve been in advanced packaging as part of my career and am very sensitive to it driving the next generation of electronics and PCB boards. It’s the key to the future of electronics growth.

MB: From the assembly viewpoint, we see issues where the tolerances for SMT assembly require bare board yields in the 98%, 99% range, and not just by visual inspection, or there are problems with printing. These problems will be even more severe with smaller components such as metric 0201s.
BB: You’re touching on the area that is exactly why we are co-located with our Flextronics Assembly Engineering Lab. Regardless of whether it’s a module, or a chip on a package, all require flawless assembly. From a Six Sigma standpoint, it’s necessary to fully control all the aspects of the process.

Ed.: For the full interview, visit http://bit.ly/14kfJOA.

As our alternative energy column comes to a close, the author contemplates the past and the future.

Readers of this magazine might have wondered what this column was doing in an electronics assembly journal. Certainly solar cell metallization and the latest photovoltaic technologies may have been perceived to be outside of the scope of traditional SMT processes. But, when this column was conceived, there was a strong indication that many conventional EMS assembly firms might jump into the solar market. Indeed, there was opportunity and a knowledge base that made this move plausible. Of course, we now know that this hasn’t happened as expected – partly because of the well-publicized solar market slowdown of the last two years, but also because the EMS manufacturing infrastructure in its current state wasn’t necessarily conducive to solar manufacturing.

So, even though many of you have appreciated this column, its relevance for electronics assembly specialists is not what it once was. Therefore, this will be my last solar column in Circuits Assembly – at least for now. Who knows? Perhaps there will still be opportunity for a unification of EMS and solar manufacturing down the road.

Even as I write this last column, there are clear indications that the solar market is headed in a positive direction. In fact, many of our company’s customers are very busy right now, so getting time on the line for new technology trials has been challenging because of full production schedules. Though but one piece of evidence, this is a very encouraging sign. What’s more, even during the photovoltaic manufacturing downturn, our company was very successful in the fuel cell market, participating as a key enabling technology, and this work continues. 

Without question, the solar industry has come out of the bottom of the trough. Exactly how the growth curve shapes up in the future and whether the market continues to accelerate at its current pace is uncertain, but there is seemingly a lot of positive news.  Take, for example, a recent report that shows solar module prices having increased for the first time in quite awhile because the demand for modules is now so high. Driving this growth are regions like China, Japan, the Middle East and North Africa, and the US.¹ The same report that highlights these regions also points to 12% gigawatt growth from 2012 to 2013 – a rate we haven’t seen since the first half of 2010.¹

Another market analysis presents market supply and demand probabilities in three parts: downside, most likely and upside.² The report points out that with the most likely scenario, end-market demand for 2012 was in the 30GW range; 2013 should be slightly improved and, by 2016, module production could conceivably be in the 50GW range. While this news is heartening, the fact remains that overcapacity is still an issue, and even though the market is growing, significant manufacturing expansion is unlikely. Until market demand exceeds the 45GW level – which could happen as early as 2014 – new capacity will not be required.

While manufacturers manage these conditions and anticipate continued increased demand, the current focus is on cost preservation. This, too, is an area where our company has played a significant and meaningful role. Over the past five years, the development and introduction of high-accuracy, high-throughput metallization platforms have helped vastly improve wafer per hour (wph) rates and, therefore, lower costs. Additionally, advances in stencil and screen technology and print process innovation have enabled reduced silver paste material use that has dramatically lowered costs. At a metallization workshop in May of this year, our company, along with the Institute for Solar Energy Research Hameln/Emmerthal (ISFH) and the Department of Solar Energy at the Leibniz University of Hanover, presented findings from our work to deliver record-low silver paste consumption. Utilizing dual-print techniques for fine-line printing, we were able to reduce paste consumption to 67mg per solar cell. Considering that just two or three years ago the average paste use per cell was between 150mg and 200mg, this is a significant cost down development.

The longer-term forecast for solar capacity expansion is quite upbeat. And, there are many opportunities for cost-preservation strategies in the current climate, too. In fact, sometimes market upheaval spawns more innovation than boom times. I remain a firm believer in solar’s future, its benefit to the global community and look forward to continuing the great work we are doing to advance solar technologies.

So while my column won’t appear in this space anymore, I am still diligently working with teams at our company on new cell metallization technology. Any questions
you have with regard to solar are welcome. Feel free to contact me anytime.

It’s been a pleasure.

References
1. IMS Industry Report, Q1 2013.
2. NPD Solarbuzz, 2013 PV Q1, April 16, 2013.

Tom Falcon is a senior process development specialist at DEK Solar (dek.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

Our annual survey finds a quarter of PCB designers are nearing retirement, but salaries have never been higher.

If a recent survey is any indication, printed circuit board designers are becoming an even more experienced crowd and have concerns about their workload, yet their salaries are increasing slightly with age.

From May 1 to June 30, a total of 421 bare board designers responded to PCD&F’s annual salary survey. The online survey covered salaries, job functions, titles, project types and quantity, benefits, education, experience, career challenges, locations, ages, and company demographics, to name some. Results are intended to provide a snapshot of the state of design industry jobs, not a meticulous scientific study.

Of the 421 respondents, just over half (50.4%) say they are senior PCB designers, down from 56% in the 2012 survey. PCB designers account for 16.9% of respondents, compared to 15% last year. Other common job titles include design engineer (7.6%), PCB design manager (7.6%), hardware engineer (4.3%), and senior engineer (3.6%). CAD librarians made up 2.6% of those responding.

As in 2012, respondents overwhelmingly say their principal job function is PCB design (including schematic, layout, placement, etc.) (Figure 1). Next is PCB engineering, with 11.9% of responses, followed by design/layout management, engineering management, and ECAD librarian.

The majority of designers continue to work for OEMs (66.3%). Another 11.2% work for design service bureaus, compared to 10% in the previous year. Strikingly, relatively few – 1.9% –  of respondents indicated they work for a contract assembler, despite the increase in those services among EMS providers.

As the 2012 and 2013 surveys have shown, for a significant portion of designers, retirement is looming. Over a quarter of respondents (25.4%) have more than 30 years’ experience in the business, compared to 21% last year (Figure 2). Some 57.7% of participants in this year’s survey have more than 20 years of experience, compared to 53% in 2012. Only 17.3% say they have 10 or fewer years’ experience, flat with 2012.

Along those lines, 24.9% of respondents are between the ages of 51 and 55, the demographic most represented in the survey. More than half (58.6%) fall between 46 and 60, compared to 55% last year. In 2013, 8.8% of respondents are 60 to 70 years old, compared to 10% in 2012, and two respondents are over 70. In the younger age brackets, 10.2% are 41 to 45, flat with last year, and 14.7% are 31 to 40, down from 16% last year. Just 7.1% are 30 or younger, and no one who responded to the survey is younger than 20.

The demographic of designers is still resoundingly male, with 89.3% of responses, up from 86% in 2012’s survey.

Top earners. With the veteran population growing in the design industry, so are salaries. The top earners make over $150,000. Nearly one-third of designers make between $70,000 and $90,000 a year (Figure 3), and 34.1% earn more than $90,000, compared to 28% last year. Of the designers who took the survey, 74% make more than $60,000, up one percentage point from 2012. Only 7.2% bring in $20,000 or less, compared to 8% last year.

While the clear majority of respondents say their salaries increased in the past year – 72%, up from 69% in 2012 – the increases were modest, with 48.2% of respondents’ salaries growing 1 to 3%. Another 14.3% say their salary rose 4 to 6%, and 6.2% report a salary increase of 7 to 10%. More than 21% of survey respondents say their salary did not change in the past year. About 7% of respondents said their salary decreased, which was consistent with the previous survey.

More than half the respondents say they did not receive an annual bonus in the most recent year (53.4%). In the 2012 survey, 56% said they did not receive a bonus. Though the frequency of bonuses appears to have improved, based on responses, the amounts are less. Of those who recently received a bonus, 55.1% say the extra cash, on average, is 1 to 3% of their current salary, compared to 43% of respondents in 2012. Another 24.4% say 4 to 7%, down from 29% last year, and 20.5% say more than 7% of their salary, compared to 28% in 2012.

A vast majority of respondents say they live in the US (70.7%) (Figure 4); this figure is slightly down from 73% in the 2012 survey. The West Coast of the US (including Arizona) accounted for 22.3% of respondents, compared to 23% last year. Another 16.9% live in the Midwest, while 16.6% are in the Northeast/New England/Mid-Atlantic. Some 8.6% of responses came from Central/Western Europe, compared to 9% last year. There were a trickle of respondents from China, perhaps owing to the survey only being conducted in English. Two designers from Africa/Middle East responded, however.

Tech trends. Technology is always advancing, but sometimes not as fast as we would think. Designers were asked what types of projects and/or technologies they directly engineer, design or lay out. The most common response? Four to 6 layer PCBs, followed by double-sided boards. Yet use of BGAs, CSPs, HDI and embedded systems are on the rise (Table 1).

More than a quarter of the designers who responded to the survey (25.2%) say they produce, on average, 6 to 10 new designs each year, down from 29% last year. Another 21.1% say they produce 11 to 15 new designs annually, up from 18% in 2012. Just over 15% produce 1 to 5, flat with the previous survey, and 11.9% say 16 to 20 new designs, compared to 14% last year. Some 10.2% produce 21 to 30 new designs, on average, annually, up from 8% in 2012. Another 16.4% produce more than 30, nearly flat with last year.

Designers are an educated group (Figure 5). More than 31% say they have a one to two-year associate’s degree; another 24.5% have some college, but no degree, for a total of 55.6%, compared to 60% in 2012. More designers this year say they have a bachelor’s degree in engineering or a related field (28.5%), up from 21% last year. Fewer designers this year reported either a master’s degree or Ph.D.

Fewer designers also say they are an IPC Certified Designer (30.9%); in 2012, this number was 33%. Of the designers who are IPC certified, 57% say they are CID; 43% say CID+.

Government/military/aerospace/avionics/marine/space garnered the most responses (again) when designers were asked which end-market they primarily design for, with 22.6%, compared to 23% who said “high-reliability products” last year (Figure 6). Communications/related systems equipment (including all phone types) is a close second, with 16.6%. Industrial controls/equipment/robotics received 13.5% of responses, and consumer electronics another 9%, down from 11% in 2012. Other end-markets are electronic instruments/ATE design and test (8.8%); medical/optical electronics and equipment (8.1%); other (6.2%); computers/peripherals (5.5%); automotive/other ground vehicles (5%), and semiconductors and related packaging (4.8%).

Designers are keeping their jobs. Some 93.3% say they have the same job as 2012, up from 91% in the previous survey. Nearly 7% were laid off in the past year, comparable with the 2012 survey.

Workload is still designers’ biggest challenge, with 51.8% stating so, up from 49% in 2012. Other challenges include technology (35.6%), nearly flat with 2012, and finding/keeping one’s job (34.9%), also flat with last year. Outsourcing received fewer responses than the previous survey, with 22.1%, down from 25%.

A large portion (72.9%) of designers who completed the survey do not have other staff members reporting directly to them. Some 18.8% say they have 1 to 5 people reporting to them, nearly flat with last year. Only 4.8% say they have six to 10 people reporting to them, and another 2.1% oversee 11 to 20 staff. Just over 1% have more than 20 employees reporting directly to them.

When asked their highest level of purchasing power, 31.8% of designers say they recommend products, down from 36% last year. Some 23% evaluate products, up from 20% in 2012. Another 17.6% have the ability to specify products, compared to 17% last year, and 12.1% approve product purchases, up from 8% in the prior survey.

Among the products and services evaluated, recommended, specified or approved, CAD software led with 78.9%. Prototype PCB services garnered 56.5% of responses, while design services pulled in 36.6%. Here’s how the rest of the list breaks down:

• Active/passive components: 30.4%
• Connectors and cables: 29.9%
• Assembly services: 29.7%
• Volume PCB fabrication services: 28%
• CAM software: 27.8%
• Substrate materials: 20.9%
• Solder mask: 20.7%
• Computers and peripherals: 19%
• CAE software: 18.1%
• FPGAs/PLDs: 15.4%
• Consulting services: 15.2%
• Solder materials (paste, flux): 12.8%
• Epoxies and finishes: 11.6%
• Test/measurement services: 11.4%

Designers still work for large firms. When asked how many staff members their company employs, 43.7% said more than 1000, up from 40% in 2012. Another 16.4% work for firms with 251-1000 employees, compared to 18% last year. About 10% work at companies with 101-250 employees, down from 13% in 2012. Other responses include 51 to 100 employees (7.4%); 26 to 50 employees (6.7%), and 25 or fewer staff members (15.7%), compared to 14% in 2012.

The distribution by company revenue was fairly even. Between 7% and 11% worked for firms with sales of less than $5 million, $50 million to $100 million, $100 million to $500 million, and $500 million to $1 billion. Fifteen percent work for firms with annual sales topping $5 billion; 13.8% work at companies with sales of $1 billion to $5 billion, and 16.4% work for firms with sales of $5 million to $50 million.

The picture of company benefits looks remarkably similar to data compiled in 2012. Leading the way again is health insurance, with 86.9% of companies offering this, and 73.9% offering dental insurance. Life insurance is provided to 72.4%, and some 67% are offered a 401(k) plan. All these figures are consistent with the 2012 survey. Other benefits include:

• Cafeteria: 44.4%
• Stock purchasing plan: 33%
• Company pension or retirement plan: 28.7%
• Exercise room/equipment: 28.7%
• Profit sharing: 24%
• Telecommuting: 20.7%
• Relocation expenses: 14.3%
• Daycare facilities: 4.3%
• Sabbatical: 4%

Many companies support educational opportunities, with tuition reimbursement leading responses at 56.1%. On-the-job training is supported by 50.6% of companies who employ survey respondents. About 45% reimburse for conferences, and about 40% conduct company classes. Mentoring is supported by 27.1%, and college classes are supported by 18.1%.

To view results of the 2012 survey, visit http://pcdandf.com/cms/component/content/article/246-2012-articles/8976-designers-salary-survey.

Chelsey Drysdale is senior editor for PCD&F/Circuits Assembly; This email address is being protected from spambots. You need JavaScript enabled to view it..