2013 Articles

The ongoing push to integrate mechanical and electrical design has now extended to electronics cooling simulation.

The latest electronics cooling simulation software has successfully integrated mechanical and board-level tools inside a common user interface. In doing so, Mentor Graphics has tackled two of today’s trends: electronic challenges and geometric complexity.

“One particular challenge is that EDA systems deal with 2D representations of the electronics because both IC and PCB design are done using schematics,” Mentor says. “PCB design tools require only the component layout and often do not contain even the most basic geometric information about the components such as component height. Detailed information about the internal geometry of the chip packages is typically unavailable.”

In developing FloTherm XT, Mentor combined the electronics cooling platform of its FloTherm thermal analysis software and Concurrent Computational Fluid Dynamic (Concurrent CFD) technology from its FloEFD product. The interface is fully configurable and scalable, adaptable to design project changes.

The new software’s library of models handles imported or CAD-generated geometries, and automatic meshing and data convergence reduce execution times. FloTherm XT also integrates with PCB design flows to reduce data translation and errors.

Mentor says the new tool enables earlier virtual prototyping, fewer design iterations, and advanced “what-if” analysis for improved product quality and faster time-to-market.

One issue is scale disparity, or the difference between the size of the physical product and that of the components and circuitry. The presence of small gaps, in the casing for example, can have a profound effect on electronics cooling, Mentor says.

This calls for behavioral models when the geometry cannot be represented directly within the simulation, as is usually the case with PCB traces on multilayer PCBs, and compact thermal models (CTMs) for IC packages to avoid having to model the internal geometry, which is often unknown.

Traditionally, thermal design has been done alongside electronic design. The use of high performance computing (HPC) infrastructure for CFD has been far less than in other industry sectors. But in electronics cooling, increased simulation precision does not translate into improved product quality. The quality of the simulation model is limited by far greater uncertainty in the input data.

For electronics cooling applications, issues relating to turbulence modeling, are rarely, if ever, the largest source of error in the results, Mentor says. It is more likely to be uncertainties in power dissipation, materials, flow rates, or interface resistances. However, turbulence can be a source of concern for some more specialized designs. The new software provides options for laminar, transitional and turbulent flows, but limits the turbulence models that are available to avoid confusion. It makes use of a general two-equation model combined with a proprietary immersed boundary treatment for near-wall effects that smoothly transitions between the different flow regimes, resulting in benchmark results said to be appropriate for electronics applications. It interfaces with existing EDA tools, and simulations can be started at the conceptual stage and continue through to implementation.

Mike Buetow is editor in chief of PCD&F (pcdandf.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

The 23rd FineTech Japan, the world’s largest trade show for flat panel displays, was held at Tokyo Big Sight from April 10 to April 12.  The following shows were held concurrently in the convention center: The International FPD EXPO, Touch Panel Japan, Nanoimprint Technology Fair and the Printed Electronics Fair.

Read more: Will Organic Electronics Be Here in 10 Years?

What effect will a loose money policy have on the Japanese PCB market?

Read more: Tripping Out Of The Gate

EMS companies showed their flexibility in 2012, adjusting to slowing consumer and defense markets.

Read more: Bend, Don’t Break: The CIRCUITS ASSEMBLY Top 50, 2012

The processes are as important as the tools.

With so many tools and techniques available, attention often focuses on the technology of ESD control; management issues don’t receive as much attention. Yet, the procedures we use to implement and manage an ESD program are just as critical to its success.

ANSI/ESD S20.20: Standard for the Development of an Electrostatic Discharge Control Program can be referred to for recommendations concerning essential elements that comprise any ESD program: program plan, training plan, verification plan and technical requirements. And ESD Handbook TR20.20 provides guidance to assist in developing an ESD program. Each facility must develop its own specific procedures to implement the plan successfully, however, and several factors come into play.

Identify and establish ESD teams. ESD problems and solutions are both multi-disciplinary and multi-departmental – crossing various functions, departments, divisions, customers, and suppliers. As such, a team approach to program development and implementation is a must. Team composition includes line employees, the ESD control program manager and department heads or other management personnel. ESD teams help assure a variety of viewpoints, the availability of the needed expertise, and a commitment to success. It is important for company management to empower the team and provide the necessary resources so that they can implement, manage and maintain the plan.

Identify your losses. With a team in place, the next step is to determine the extent of company losses to ESD. These losses may be reflected in receiving reports, quality assurance (QA) and quality control (QC) records, customer returns, in-plant yields, failure analysis reports, and other data gathered over time. This information not only identifies the magnitude of the problem, but helps to pinpoint and prioritize areas that need attention. In the long-term, documentation of losses not only helps identify problems, but provides the reporting necessary to modify the program and to calculate return on investment. Sometimes the information about losses is not readily available, and the requirement for an ESD program is driven by customer requirements. The customer may want assurance that it is not going to receive product that has been exposed to electrostatic influences during handling or manufacturing operations. 

Identify sensitive items. Items that are sensitive to ESD (components, assemblies, and finished products) and the level of their sensitivity should be identified. Items can be tested in-house, use data from suppliers, or rely on previously published data. Sometimes it is necessary to establish a baseline or set a level of your own based on evaluation of your processes. 

Evaluate your facility and processes. Look for areas and procedures that may be contributing to defined ESD problems, such as static-generating materials and personnel handling procedures for ESD-sensitive items. Process assessment involves measuring the levels of static electricity within your processes to help define the level of risk for damage to susceptible parts handled within those processes.

Establish and implement procedures. Next, begin to develop and implement the appropriate procedures that will help solve ESD problems identified. ANSI/ESD S20.20 can be used as the basis for a program plan. Prepare and distribute written procedures and specifications so that each employee has a clear understanding of what procedures must be followed. Fully documented procedures will assist in achieving ISO 9000 and S20.20 certifications.

Train personnel. Train and retrain personnel in ESD control procedures. Proper training for line personnel is especially important, as they are often the ones to implement program procedures on a day-to-day basis. A thorough understanding of what ESD controls are in use, and why they are needed, will have a significant and positive impact on proper long-term implementation of the ESD control program. Again, training plan guidance is in ESD Handbook TR20.20.

Evaluate, adjust and provide feedback. Conduct periodic evaluations of the ESD program and audits of the facility to verify that the program plan implemented is working. Such evaluations can demonstrate whether the program is successful and validate the company’s expected return on investment. Weaknesses in the program can be identified and corrected. As areas that need work are found, make the necessary adjustments to keep the program on track.

Remember to provide both reporting and feedback to management, the ESD team, and other employees. Management will want to know that the investment in time and money is yielding a return in terms of quality, reliability and profits. Team members should be recognized and rewarded for a job well done and kept informed of future ESD control program plans. Other facility employees will want to know that the procedures implemented are indeed worthwhile.
An effective ESD program consists of much more than wrist straps and shielding bags. Effective management and implementation procedures provide a solid foundation on which to build your ESD control program.

This column is written by The ESD Association (esda.org); This email address is being protected from spambots. You need JavaScript enabled to view it..

Reusing circuits using advanced block hierarchy.

Do you use hierarchy in schematic designs? In layouts? If you think I’m asking if you carry a big stick and issue decrees upon your peers, read this. Many engineers and designers shy away from hierarchy because it’s more complicated, but it only takes a little bit of extra thought to get it right the first few times around. Once designs are using blocks, they become much easier to check and maintain. They also save a lot of design time, mostly the wasted time copying circuitry needlessly. ECOs are also much faster, because one change to the lower level design immediately updates all contexts of the top-level design. There’s no need to change every single one of the repeated circuits.

Once traditional hierarchy is in place, more advanced options become available. Many CAE software applications contain the ability to tie a block design directly to a layout block, opening possibilities for organizing both schematic and layout in a more orderly and easy-to-track fashion. This is often referred to as physical hierarchy, and it can be especially useful with design reuse circuits and array types of designs. With array designs, blocks can be organized inside other blocks (Figure 1) in nested hierarchy, making it possible to boil down a very large design into just a few physical blocks to add and maintain.



Last, there is a lesser-known hierarchical capability in some schematic software applications that could be useful. This is the concept of a frame, or a virtual block. This is a block that has no block symbol. It is designated by a border drawn around the circuitry meant to be a block, which is most often tied to a physical block in the layout. This kind of hierarchy is especially useful for smaller schematics; if there is only one page of circuitry representing a board design, it can be broken down into any number of blocks without requiring that the circuits be broken up into separate sheets with one top level design to contain the block symbols. Essentially, the one page of circuitry remains one page instead of three or more. Imagine, for example, a block array design. If there is only one small page of simple circuitry (Figure 1), a virtual block could be drawn around it, and then the block can be assigned a number of placed blocks in the layout, a starting placement value, and an X and Y offset per block for automatic placement of the entire array in the layout. So 1024 block cells would be represented by a one-page schematic.

Traditional block hierarchy. To understand how to use the more advanced types of hierarchy, it helps to examine the commonly used traditional hierarchy. Most readers probably know hierarchy in a schematic design is the process of using “block” symbols to represent a section of circuitry in a design. These symbols represent a separate design from the main, or “top-level,” design, with pins that represent the names of nets that connect from the block design into the main design. Often times, the separate designs are schematics borrowed from previously proved circuits, which are then incorporated into an entirely new design. Blocks are especially useful when the circuitry is repeated over and over in the resulting layout design; this scenario is referred to as replicated hierarchy, meaning that the same block is copied and placed down two or more times.

Use of traditional logical hierarchy opens up more options for completing designs. Portions of designs can be divided up among a team of engineers, with the main or “host” design ultimately owning the finished copy of each person’s work. These design portions can be sent off for simulation or testing without requiring the entire design to be sent off, permitting progress to continue in other areas of the design. Dividing designs into blocks can also help floor-planning for the layout, where specific functional areas of the layout are grouped logically.

But the most obvious advantage of using blocks is seen with replicated hierarchy. When a block symbol is placed two or more times in a schematic, there is still only one underlying schematic. The schematic application takes care of displaying each block’s “context,” which holds unique references and property values for every component. So while there is one underlying schematic, the same component viewed through one block has the same number of references as there are uniquely placed blocks.

Physical block hierarchy. Building on the concept of logical hierarchy is physical hierarchy. Once a schematic is defined using hierarchical blocks, those blocks can then be assigned directly to a block in the layout. The various CAD systems handle this concept differently, with some having actual block geometries in the layout and others simply defining the physical “block” area using attributes or properties. This method is helpful for layouts with replicated blocks, because once the layout block is created, it can easily be placed again and again. The creation and editing of the layout circuits is much simpler, because changes to the replicated block are made at the block level, which removes the need to make repetitive changes across all copies of the block.

Virtual blocks. Building on the concept of physical hierarchy is a whole new level, the virtual block, or frame. As an example, imagine a simple design with only one page of circuitry. But this circuit is placed into an array design 1024 times. Using the other forms of hierarchy, this would require 1024 block symbols to represent the one page. With a virtual block, however, this can be programmed directly on the schematic page. Figure 3 depicts an example of a block array schematic. The circuitry to the left is the main level circuitry, while the shaded box indicates the virtual block. This block is defined with properties specifying the number of times it is placed, and the X and Y offsets for each block. Viewing a block context is the same as though the virtual block were a block symbol.

[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]

The virtual block can be used for many kinds of designs, but another good example is a hybrid design with separate circuits for the cavities in the design. The wirebonds for a chip, for example, would be represented on the schematic with a virtual block surrounding the chip. The block would have virtual block pins at the location where the net crosses the block boundary. These pins create a split in the net that is exactly the same as a split in a net across traditional hierarchy, but without requiring the manually defined block pin. This permits the nets from the pins on the chip to traverse up to the main level design, but in this case, the hierarchy is all on the same page. This result of using virtual blocks tends to be a much simpler schematic design, but it also ensures greater design integrity in the layout since it is conceptually easier to track the connections of the design.

In summary, the use of any flavor or hierarchy almost always serves to reduce complexity, speed design cycle time, ease ECOs, and increase opportunity for design reuse. While the concept of hierarchy is more complex, the resulting design is not. Be sure to weigh these options before beginning a new design, because once the plan is laid, it can become much easier to accomplish the task.

Abby Monaco, CID, is product and marketing manager for Intercept Techology (intercept.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

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