Proper measurement is a complex but necessary process.
An oft-asked question is, “Does my process generate an electrostatic charge, and if so, how much?” If the ESD program manager is looking for a simple “yes or no,” the answer may be disappointing. If, however, the ESD program manager is making an argument for the complexity of ESD, then the answer proves the point.
Static control would be much easier if a “yes or no” question led to a successful ESD control program. However, oversimplification often creates more problems than it solves. In ESD control situations, this is more the rule than the exception. While ESDA standards and other documents such as ANSI/ESD S20.20 and ESD Handbook TR20.20 can provide guidance and starting points, each process and facility is unique. Therefore, the rule to successful ESD control is not guessing, but measuring.
Why measure? Why take the time to measure the processes or materials? Several reasons. Measurements will aid in ESD control from beginning an ESD control program through to program maintenance.
First, measurement defines the problem accurately. From an ESD perspective, most environments are unique. What might cause an ESD problem in one environment may not cause a problem in another. Measurement helps identify whether a problem exists in a given environment. Then, those measurements provide concrete documentation for obtaining the financial and personnel resources needed to solve the problem.
One can arrive at more accurate solutions through measurement. For example, if the insulators in the environment are not producing electrostatic fields, why purchase ionizers to solve a problem that doesn’t exist?
Once measurement has accurately identified the problem, prioritize those areas that require the most attention and select the appropriate solutions. The more specific the knowledge of the problem, the more successful the solution will be. For example, knowing that a material has a resistance of 106-109 helps prevent confusion that can occur with the imprecise use of terms such as conductive or dissipative.
Once ESD control measures have been selected and put in place, assess progress and results through measurements. If the solution reduces electrostatic potentials on personnel from 1,000V to 50V, the solution has been effective and can be checked regularly to ensure that it continues to work.
Where to start. What gets measured in the facility? Generally, those processes and materials suspected of generating electrostatic potentials or charge: personnel moving in the area, conveyor systems, display monitors, insulators, carts, etc. After ESD control processes and materials have been selected, they should also be measured to ensure the items function properly and that they continue to function properly.
Measurement equipment. Generally, two types of measurements should be considered: electrostatic fields or potentials and resistance or resistivity. Some relatively inexpensive equipment options are resistivity meters, resistance test kits, and electrostatic field meters. For process and facility evaluation, what’s of primary interest is an indication of whether a material or process generates high or low levels of electrostatic charge. Frequently, what is wanted is an indication of whether a material has ESD properties, and will remove electrostatic charge when connected to ground.
Material evaluation and qualification may merit laboratory level tests, which may require more precise instrumentation.
ESD control doesn’t often fit into a simple “yes or no” framework. When observations and intuition are supported with data, surprises and guesswork can be eliminated. By making a practice of measuring, the implemented ESD control measures have an increased chance of effectiveness and success.
This column is written by The ESD Association (esda.org); This email address is being protected from spambots. You need JavaScript enabled to view it..
A new wirebond PoP achieves nearly 1000 interconnects at 200µm pitch.
New generations of thin notebook PCs such as the ultrabook are changing the way memory is used in portable electronics. The traditional SO DIMM is far too big and bulky to consider for these slimmed down PCs. In an effort to minimize the profile of the electronics assembly within the ultrabook product, manufacturers have resorted to soldering the memory directly on the circuit board.
The 16 single-die SDRAM packages on the ultrabook PCB are arranged in two rows of eight. The two-row 16-package memory configuration requires a rather complex interconnect scheme. Such complexity forces adoption of higher density circuit board technology.
Three conventional package configurations are currently in wide use for stacking the high-performance SDRAM (the opposing face, top face-up, bottom face-down; staggered stack RDL modified for edge bond; and the face-up, RDL modified for edge bond, Figure 1). All these configurations suffer from long connections between die pads and the package ball-out.
Two new multi-die DRAM package technology families are designed to solve specific system integration problems of growing importance in the industry. The first (Figure 2), called the Dual Face Down package, is for high-density and high-performance DIMM applications. Designed to optimize PCB layout, high-speed signal integrity and thermal performance, these dual die packages are made using standard face-down process.
The second (Figure 3), called the DIMM-in-a-Package memory device, accommodates four devices in a single component (Quad Face Down), and is specifically targeted to the new ultra-slim form-factor notebooks such as ultrabooks and tablets. Using a common ball-out scheme optimized for efficient PCB layouts on low-cost through-board via PCB technology, this same ball-out accommodates DDR3x, DDR4x and LPDDR3 devices.
Common to both solutions is the use of existing high-volume wire-bond-based face-down window-BGA DRAM assembly infrastructure. No new capital equipment is required for the assembly operations. No re-distribution layer (RDL) is required, and using common wire-bond BGA assembly, the unique structures offer single-pass line assembly.
Both families offer low profile due to the face-down structure. The face-down die orientation minimizes wire-bond length and avoids the need for thick encapsulation above the die, in contrast with face-up wire-bonding. The result is a dual-die package or quad-die package less than 1mm thick. The thin profile coupled with the die not being stacked directly atop one another offers thermal advantages (Table 1) in addition to the short electrical pathway and cost advantages.
[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]
DFD technology. Unlike traditional stacked-die DDPs, the DFD features separated DQ signals. The construction uses a variant of the high-volume window-BGA face-down package; a live die and a spacer die are mounted facing the substrate, and a second bonding window is added. The second memory die is stacked above the second bonding window in a shingle-like configuration. The result is a 104-ball 11.5 x 11.5 x 1mm package with 0.8 x 0.8mm ball pitch. Detailed manufacturing cost models show that the DFD costs 1.8x the cost of a single die package (SDP), translating to the cost per die actually being lower than for an SDP.
One key design feature of the DFD is the placement of the Command/Address (CA) signals in the center of the package. This solves the well-known cross-tie stub problem associated with standard single, double and quad die packages used on double-sided assemblies by decreasing the distance the cross tie stubs must be routed in the breakout region.
Another feature of the DFD is the ability to route the CA global bus in a single layer in a standard DIMM PCB process. This avoids layer-to-layer timing skew that impacts operating frequency.
High-performance quadrank RDIMMs and Hypercloud DIMMs have been manufactured and demonstrated using the DFD technology. Quadrank RDIMMs have been shown to operate reliably at 1600MT/s DDR3 rates using two Quadrank RDIMMs/channel. Single quadrank DFD-based RDIMMs have been demonstrated at 1866MT/s.
DIMM-in-a-Package. Ultra-slim notebook and tablet devices have largely been turning to solder-down single-die packaged memory and expensive HDI buildup PCB technology. The form factor of the shrinking vertical dimensions no longer accommodates SODIMMs.
The DIMM-in-a-Package memory device has the functionality of an SODIMM (Figure 4), including an optional SPD/TSE in a single BGA, and is configurable as a single x64 or a dual channel x32 memory system in a package. The package is a 407-ball BGA using 0.8mm pitch and is 17.5 x 22.5 x 1mm. This technology features a common compatible ball-out that supports DDR3x, DDR4x and LPDDR3.
The packages using this common ball-out can be constructed using a variety of methods, including four-die structures using face-down window BGA assembly methods. This leads to a very efficient manufacturing flow; all the die are placed in a single operation and from the same wafer region, and all are wire-bonded in a single operation offering the same strips/hour assembly throughput on the same machinery as standard single-die packaging. This is the method used for building high-volume DDR3 and DDR4 versions of the novel packages, as well as the center-bonded x16 LPDDR3 version. The x32 periphery-bonded LPDDR3 versions are assembled in a two-die face-up wire-bonded configuration featuring one-pass die placement and one-pass wire-bonding as for the four-die face-down versions. The fact that within the same package the die all came from the same region of the wafer has demonstrated great binning yield. Detailed cost models indicate the QFD assembly costs 3.8x the cost of an SDP to manufacture. Again, on a per-die basis this is less than for an SDP and 2.4 times less than the QDP (Table 1).
For the system OEM and ODM the benefits are numerous. A key design goal was efficient PCB layout using a standard low-cost Type 3 PCB. Additionally, when using the second-generation ultrabook CPU that offers co-support of LPDDR3 and DDR3, a single low-cost Type 3 PCB can be designed supporting either type of memory. This greatly reduces the cost of design.
Using previous generation layout guidelines, a 40% reduction in area was attained by migrating to a 12-layer Type 4 design made using single-die packages to a low-cost Type 3 PCB using the novel package devices.
The novel package is not limited to solder-down memory applications. Using board-to-board connectors, a dual-channel module can be constructed that is the same XY size as an SODIMM but sits no higher than 3.5mm above the lower PCB. Using double-sided assembly, a 16-die dual-rank dual-channel module can be constructed.
Package-on-package stacking. Current PoP modules have limited data I/O (~32-64), and a new technology is needed to meet the high I/O (128-512) requirements. The processor-memory bottleneck must be addressed through very wide I/O for high bandwidth while consuming low power. Bond Via Array (BVATM) PoP offers bandwidth communications with wide I/O, low power memory chips using conventional wire-bond technology and existing materials and infrastructure.
Figure 5 illustrates the Bond Via Array (BVA) wire-bond array interconnect concept. The main feature is that the BVA interconnects (freestanding wirebonds) bridge the top surface of the bottom package to the bottom surface of the package mounted on top.
The mature wire-bonding technology offers very fine-pitch, and freestanding wires are formed using proprietary processes on conventional wirebond equipment. The wirebonds can be fine pitch, and can extend in length to any desired value, thus achieving high aspect ratio (height-to-diameter ratio greater than 10).
The I/O capabilities are tabulated in Table 2. For a given 14 x 14mm package and assuming a 1mm peripheral width for I/O, up to 1440 interconnects can be formed at 0.2mm pitch. These numbers of I/O are enough to meet future wide I/O memory requirements.
A daisy-chain prototype of 432 I/O BVA PoP test vehicle was designed and fabricated that measured 14 x 14mm with two perimeter rows of copper wires at 0.24mm pitch with a wire diameter of 50µm and a height of 0.4mm. This test vehicle has an interconnect aspect ratio (height/diameter) of 8 and pitch ratio (height/pitch) of 1.7. These conditions exceed by far any existing PoP technology.
The vehicle consists of stacking a memory package over a logic package with BVA interconnects. The top (memory) package is similar to current memory packages, including high I/O BGA. The bottom package has the logic device in a flip-chip format, with the BVA wires around the periphery. The molding with wires is applied differently. Finally, stacking is done using conventional surface mount technology (SMT) with the condition that the top memory package has fine-pitch BGA. The four manufacturing process steps are described below.
The freestanding wirebonds are the most critical step of the process of the BVA PoP. Forming the wirebonds with the tips having good positional accuracy (X and Y) and uniform height (Z) is important in enabling very fine pitch and high yield package assembly. Figure 6 shows bottom package substrate with the flip-chip attached logic chip and BVA around the periphery.
Once the wirebond connections are made, the molding is applied to the logic package, while exposing the BVA tips with a consistent desired height. A film-assisted mold technique was used here to expose the tips. The process uses mold cavities only slightly deeper than the formed copper wires. When the mold is clamped to the substrate, the tips of the copper wires are pushed into the mold film. The mold cavity is filled with the molding compound. After mold cure and the film removed, the package reveals the wire with exposed tips about 0.12mm ±10µm.
To achieve very good solder stacking results, the wire tips are cleaned after molding and various techniques such as wet blast and chemical etch were used. The best conditions were obtained with wet etch (Figure 7).
Finally, the stacking of the memory package on top of the logic package is performed (Figure 8). This process is very similar to conventional PoP assembly where solder paste is printed on the main board; the logic package is placed on the board; the memory package is dipped in solder flux and placed on top of logic package, and the stack is reflowed along with other components on the board. Reliable joints were obtained across all interconnects over the whole package (Figure 9).
Extensive reliability tests were performed on the PoP stack, and the results are shown in Table 3. The tests illustrate the high reliability of the BVA process. It is worth noting that the drop test was extended up to 128 drops without observing any failures.
[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]
The copper-tin diffusion between the copper wire and the solder ball was studied by an accelerated testing of the amount of intermetallic formation under high-temperature storage test (3x solder reflow cycles followed by 230 hr. at 175⁰C). The copper wires were coated with palladium to stop the intermetallic formation. Figure 10 shows that wet etch method has not damaged the wire tip palladium coating, which has served as an effective barrier against intermetallic growth. In the contrary, the wet blast method has damaged the palladium coating, leading to extensive intermetallic growth.
Summary
The XFD and the BVA technologies discussed here provide enough headroom in interconnectivity and provide low power bandwidth to bridge today’s die or package stacking technologies for many years to come. These two technologies are available today and can be easily manufactured using standard available infrastructure.
Benchtop was in and integration was all the rage at the annual North American trade show.
At IPC Apex Expo this year, small was big.
The annual trade show, the largest assembly equipment event of its kind in North America, kicked off in late February to strong crowds and a positive vibe that belied the unseasonable chill in the San Diego air.
A number of products were introduced that will challenge previous designs for market share. Universal Instruments, Panasonic, Europlacer and Fuji were among those with new placement machines. Speedline showed the latest Camelot dispenser and Momentum printer, both of which are smaller than previous models. BTU proudly discussed Dyanmo, a lower wattage, smaller platform for convection reflow soldering. On the test and inspection side, several benchtop analyzers and testers were unveiled by companies big (Agilent, CyberOptics) and small (ASC).
As with last year, sensors and lasers are all the rage. Precision and speed often improve on different curves, and judging by the new machines this year, the current emphasis is more on the former. And many equipment vendors have retooled their offerings for the high mix, high complexity market.
Floor traffic, always the arbiter of a show’s success, appeared steady throughout the first day, never overwhelming but always busy and noisy. The second day started slower than the first before picking up in the late afternoon, giving exhibitors more time to dwell on the state of the industry economy. Day 3 was fairly quiet.
Several exhibitors noted that visibility remains clouded for 2013, with those supplying to the automotive sector the noticeable outliers. David Wolff of bare board distributor NCAB noted a change in supply chain practices, saying that OEMs are “absolutely taking control of (bare) boards again.”
Software
Aegis very proudly rolled out FactoryLogix, a software suite aimed at coordinating the entire manufacturing enterprise outside of accounting and R&D, including box build and system integration. The new suite tracks NPI progress, and can be adapted to individual manufacturing sites around the world. It also handles mechanical CAD as well as EDA. And, it’s configurable, but doesn’t require programming. As president Shaun Black explained, “We wanted to get the customer integration costs – such as coding – out, and the configuration in.”
Printing/Dispensing
PVA rolled out the VPX-2K 2-component dispensing pump.
Speedline’s Momentum Compact printer shrinks the footprint of the previous generation. And its new Camalot Prodigy has a narrower footprint but loses none of the functionality, boasting a 30µm accuracy at full system speed, and coming in single or dual lane versions.
DEK refined its VectorGuard stencil, increasing the tension some 45% to make it easier to print 01005 components.
Asymtek is adding a UV curing oven that features an arc lamp instead of microwave as a heat source.
Placement
Universal’s Fuzion was likely the most talked-about new placement platform. It features two head types with overlapping component capability, meaning engineers won’t need to change out the heads. It supports up to 144 feeders, which is a big jump in capacity, and reportedly has a changeover time of 15 to 20 minutes. The IPC-9850 rate is up to 30,000 cph, and the component range is 01005 to 150 x 150mm, depending on which machine is used. All in all, a very flexible new mounter has arrived.
Panasonic also had an interesting development with the AM100, a single head (single beam) mounter capable of placing components ranging from 0402mm to 120 x 90 x 28mm, large connectors, odd-shaped parts, and advanced packaging types such as PoP. It also featured non-stop changeover, allowing the next product to be prepped while production is running.
Hitachi’s Sigma F8 was another machine that is forcing a lot of functionality (four 15-nozzle heads) into a smallish (1,280 x 2,240mm) footprint.
It wasn’t all just surface mount. Panasonic debuted the AV123 axial inserter, which features 30,000 cph performance on a small (there’s that word again) platform.
Juki’s Bob Black indicated a new JM series would be out in June. Juki also happily accepted GKG’s 2012 Distributor of the Year award.
Siplace and Panasonic joined Universal as placement companies indicating growth in 2012.
Soldering/Materials
ECD has a new sensor-based system that aggregates humidity data from up to 25 points in the factory and consolidates it in a mobile app. FCT Assembly discussed NanoSlic, a cylane molecule-based nanocoated stencil said to retain the coating longer than phosphorus-based versions. (Expect to see more cylane-based flavors as the second-generation nanocoats appear.) It’s due for release in June. Count DEK among those that expect to see more coatings introduced, reporting “great results” by customers.
BTU’s Dynamo could be a game changer. (We say “could,” because the machine won’t be shown until April.) It’s a new convection reflow platform with 8, 10 or 12 zones, capable of running air or nitrogen, but with 20 to 25% less energy use than its Pyramax cousin. BTU cut the energy by reducing the number of blower motors in the heater section, instead placing one outside the chamber where it can handle two zones at once.
Finetech showed a slick tool for reworking package-on-package and QFNs.
It’s been awhile since solder material companies used a trade show to roll out new products. Instead, they leverage the events to formally announce products that were developed for specific applications or customers, in some cases, months or years earlier. Apex was the first show we saw Enthone and Alpha under their new corporate banner, Alent. There was one revelation, however: Henkel is rebranding its surface mount materials under the Loctite name.
Finally, the IPC-A-610 meeting drew 74 attendees, a big number even for the IPC’s largest task group. Of some concern, it appears the solder types have been removed from the latest J-STD-006, rendering the document as a listing of solder alloys, but not much more.
Test/Inspection
As users grapple with smaller products and tighter test access, the test strategy is inherently changing. Boundary scan is becoming more prevalent, as is BIST for chip-to-chip communication.
CyberOptics, ASC (AP500, a fully automatic benchtop 3D SPI), and Newly (n=1 first-article inspection, plus board resistance and capacitance checks) were among those pushing smaller footprints.
Koh Young has a deal with KIC to jointly develop a tracking system to report profile and joint data, which then will be displayed in Koh Young’s pre- and post-reflow results.
Mirtec’s switch to CoaxPress cameras boosted the speed of its MV-9 series, which includes all LED and 2D/3D AOI, to 25 GB/sec., up from 5 GB/sec.
Nordson Dage has a new, undisclosed platform due out at Nepcon China.
Fabrication
We wish there was more to discuss on the fab side. As noted in past years, the Asian-based trade shows (JPCA, CPCA, HKPCA) are the top sites for developments in printed circuit board fabrication. There were, however, a couple of developments that caught our eye.
Remember the ESI mechanical drill team? They are regrouping at Interdyne, and the early results are impressive. Consider a granite base, six-head mechanical drill with a so-called laminated “wing” that moves in the Y axis while the spindles move in the X. The linear motors are tied directly to the 250km spindles. The new drill uses standard bits and reportedly is capable of 2 mil holes at a rate of 1000 hits/min., and can drill a 441 mil backpanel with 90 mil thick copper at 110 hits/min. When did the last new drill technology come out?
Also, Rainbow Technology discussed its automated vertical develop/etch/strip line, which runs on 4kW of power, has full automatic handling, and requires no solvents. The throughput is 90 panels/hr., and beta testing begins this year.
As always, the show is too large to detail every new development here. For the full list of new assembly products and materials, go to http://www.circuitsassembly.com/cms/ipc2013.
While Apex likely remains second to Productronica as a site for assembly equipment launches (its fabrication-based Expo half has long since ceded that designation), we did note more than a few exhibitors reporting they were holding launches until Nepcon China in late April. Outliers or the start of a trend? It’s something to watch.
High Hopes for 2013 NPI Winners
The annual Apex trade show represents the honorary start to the new year. It’s also an end of sorts: the culmination of the rookie year for products introduced at the previous Apex.
Each year at Apex, PCD&F and CIRCUITS ASSEMBLY announce winners of the New Product Introduction Awards. The NPI Awards recognizes leading new products during the past 12 months. An independent panel of practicing industry engineers selects the recipients.
This year’s electronics assembly equipment, materials and software winners are Microscan (Mini Hawk Xi); Speedprint (SP710avi); Count On Tools (ezLOAD PCB Support System); Austin American Technology (NanoJet Aqueous Inline Cleaner); BPM Microsystems (2800ISP In-System Device Programmer); Nordson Asymtek (NexJet); Mirtec (MV-9 2D/3D In-Line AOI Series); Acculogic (Ultimate Accuracy Package for Flying Scorpion); Multitest (InStrip 3D); VJ Electronix (Vertex II X-Ray Inspection System); Parmi (SPI HS70); Nihon Superior (SN100C P604 D4 Solder Paste); Count On Tools (Stripfeeder .mod Series); Universal Instruments (FuzionXC2-37); Rehm Thermal Systems (Vision XP 934 Quad Lane Convection Reflow Oven); ACE Production Technologies (KISS-205 Selective Soldering); Kyzen (Aquanox A4639 Aqueous Solution); Cogiscan (TTC Middleware); Viscom (SPI-AOI Uplink); EVS International (EVS 10K Solder Recovery); FCT Assembly (NanoCoat Multilayer System); Air Vac Engineering (PCBRM100); AIM (NC277 Liquid Flux), and CGI Americas (Newly n=1 First Article Inspection System).
The winners of the PCD&F NPI Awards for PCB fabrication are Nordson March (FlexVIA Plasma System); Rogers (RO4835 Laminate), and Dow Electronic Materials (Microfill THF-100 Electrolytic Copper).
“Each year there’s a few true, exciting innovations,” said Mike Buetow, editor in chief of PCD&F and Circuits Assembly. “We are thrilled to recognize these companies for their efforts.”
Mack, ESI, Naprotek 2013 SEA Big Winners
CIRCUITS ASSEMBLY on Feb. 19 announced the winners of its 2013 Service Excellence Awards for EMS providers and electronics assembly equipment, materials and software suppliers. Circuits Assembly recognized companies that received the highest customer service ratings, as judged by their own customers, during a ceremony at the IPC Apex Expo trade show.
In the EMS category, the overall winners were Mack Technologies (sales of $101 million to $500 million), Electronic Systems Inc. (sales of $20 million to $100 million), and Naprotek (sales under $20 million).
The EMS companies with the highest scores in each of five individual service categories also received awards. (Overall winners were excluded from winning individual categories.) In the small-company category, ACD, Spectrum Assembly, and NexLogic Technologies tied for dependability. ACD also won for quality, and tied Pride Industries, Spectrum Assembly, and BESTProto for responsiveness. BESTProto and ACD tied for technology, while Pride Industries took home the award for value. For firms with revenue between $20 million and $100 million, Western Electronics took top honors for dependability and responsiveness. Applied Technical Services tied Sparton Electronics for value. Western Electronics and Applied Technical Services shared the top spots for quality and technology.
For EMS companies with revenue between $101 million and $500 million, EPIC Technologies swept all five individual categories.
Electronics assembly equipment award winners were Assembléon for pick-and-place; Speedprint Technology for screen printing; Kyzen for cleaning/processing materials; Mirtec for test and inspection; Nordson EFD for materials; Nordson Asymtek for dispensing, and KIC for soldering equipment. Customers of SEA participants rated each company on a scale of 1 (poor) to 5 (superior) in five service categories. – CD
CircuitHub is banking that the time is now for a user-driven parts library.
Ed.This is the latest in a yearlong PCD&F series highlighting promising new enterprises in printed circuit board design.
CircuitHub was founded in 2011, but its origins are much older. While designing boards eight years ago, Jonathan Friedman noticed that life at an engineer’s desk was inefficient. As Friedman says, there are three views of a part: logical, physical and manufacturing. The first two are handled well by CAD tools, the last by manufacturing tools, but the tools don’t communicate well at all, leaving what he calls “the great chasm” in between.
“You have two domains in play – engineering and manufacturing – each with their own libraries. And what you want is one library that can bridge both domains,” he says.
The revelation led to a series of academic papers, including one presented at IPC Apex Expo in 2011, followed by the launch of CircuitHub, whose first offering was rolled out in late January.
That product, a universal parts library, has been on the minds of designers and developers for years. It’s the Holy Grail for designers: a one-size-fits-all solution that frees them from the tedious work of library development and allows them to concentrate on the higher value layout work. (In a PCD&F survey released in December, 93% of the 451 designers responding said their CAD tools’ library creation capability is “very” or “moderately” important.) It’s also been something of a bottomless pit, as many software engineers have tried to solve the problem, with varying degrees of success.
But while labeling library creation as a huge problem, Friedman says it’s not so much intractable as it is inefficient. And, apparently, age-old. “The medium of exchange between the manufacturer and user has not evolved since 1950,” he says. “In those days, the component maker put together a datasheet and handed it to the person who was going to use it. Here, 65 years later, we have the PDF.
“Transferring information via digitized paper datasheets creates tremendous redundancy. Either the designer redrafts the data from the sheet by hand, or they go to Google and try to find some dubious third-party download. Either way, they are going to get burned.
“There’s no reason you can’t have first-run success. There’s no reason you should have a situation where the footprint is wrong, or where the footprint isn’t correctly matched to the symbol. These are secretarial issues, data entry problems. We are all creating the same data from the same datasheets in order to use the same parts from the same manufacturers!”
His enthusiasm for simplifying the libraries is just one of the facets that sets Friedman apart. There traditionally haven’t been many Ph.D.s designing printed circuit boards. Going back through 15 years’ worth of our salary surveys, the percentage of designers who identify themselves as holding doctoral degrees has held fairly steady at less than 0.5%. Friedman holds a doctorate in electrical engineering from UCLA. Between stints running four companies, Friedman also has consulted widely in signal integrity, mixed-signal and embedded systems, and put some 100-odd designs into commercial use. (Andrew Seddon, cofounder of the Silicon Valley-based company, also has 10-plus years of experience as a design engineer, hardware entrepreneur, and embedded systems consultant.)
But there’s a large gap between knowing design and standardizing footprints. Through the years, a number of companies have tried to tackle libraries: Valor, PCB Libraries, WikiComponents, plus most CAD vendors, a fact Friedman readily acknowledges. But he thinks CircuitHub has latched onto a solution that automates the development process, while also divorcing it from the CAD tool.
“Universality has been a struggle. We tackle that problem on both ends of the scale. Chip makers want to support all the tools, but there is a huge maintenance cost and liability incurred with each maker supporting all of the formats directly. On the other end, you have the assembly facilities where [footprint accuracy] might be about how good your pick-and-place machine is. These are decisions that affect the design, but are not made until later in the design cycle. And in the middle you have the design engineer who doesn’t want to spend half of his or her day just dealing with part data.
“Our universal format solves the chipmaker’s dilemma, permitting write-once, support-all symbols and footprints and our templates built in parametric data based on IPC-7351. That allows precise control of factory tolerances without having to redraw anything – solving the assembly-end of the problem. In the future, you would be able, based on the factory, to come back and have the footprint customized around the tolerance automatically.
“We have a model called automation, collaboration, moderation. We use proprietary algorithms and data sources to eliminate nearly all of the data entry work, the community provides peer-review, and conflicts go to a team of professional moderators. We further believe that it must be free and not tied to any one EDA vendor.”
Crowd-sourcing, of course, has historically been problematic. Wikipedia works because it’s so broad, and has many contributors. PCB design is a fairly narrow area. Yet Friedman is optimistic he will succeed. “The encyclopedia is hit or miss. That encyclopedia must have the content you want to know when you want to know it, or its value drops off pretty quickly. CircuitHub is very different. It’s not an ‘all or nothing’ proposition. Let’s say that CircuitHub’s library only covers 80% of your design; you can do the remainder with your existing local library. But if you don’t have it locally and you have to add a huge BGA with lots of I/Os – well, you can just add the missing part to CircuitHub in a matter of seconds. It otherwise might take 40 minutes to draft that same part directly in your EDA tool.”
In short, he says, CircuitHub’s library provides value, even if no one else uses the platform. Because symbols and footprints are paired up, it simplifies library data management. It’s also portable across tool flows.
There is, however, a user validation aspect that is typical of many crowd-sourced platforms. Users can view who authored a symbol or footprint, and can learn whose work can be trusted. “Peer review is a powerful motivator. When you get recognition for excellence, people tend to excel more,” Friedman says.
The rub for many developers is that smaller users don’t have the funds or time to develop large custom libraries, while larger OEMs see their libraries as part of their IP. The latter uses teams to develop their own, based on their internal manufacturing processes or those of their contractors.
As Friedman correctly notes, time spent on library management is time away from designing product. “Everyone’s library data derive from the same origin, the datasheet, so you aren’t going to create a lot of unique high-value IP this way.”
Citing an example of an LED that can be installed on its side, Friedman points out the part may have multiple representations depending on the orientation. “You can end up with a symbol that’s a valid representation of a part, and a footprint that’s a valid representation of a part, but a mismatch between the two. CircuitHub prevents these kinds of errors by sharing lessons learned instantly and automatically among users once someone notices a problem. We’re all in this for the same end: electronics that are easier and safer to design. And with the IPC tolerancing built-in, users can ‘tune’ a part for a specific contractor.”
Besides the accuracy of the parts (and the quantity available, of course), IP protection is a key issue. The Universal Parts Library notifies all users affected of any changes to a part. What it does not do, however, is update users to changes to an individual’s library. Friedman allows that it could be possible for someone using cluster analysis to work their way back to see what part a very active designer might be using at a certain point in time, but stresses doing so would be very difficult. CircuitHub also is considering a model where it charges users for the right to keep their custom edits private.
One security problem CircuitHub does grasp is the reluctance of companies to entrust all their IP to someone else’s hands. That’s a fundamental hurdle for cloud computing, and Friedman thinks the model by which only the standard data – that is, the footprints and symbols – reside in the cloud, while the unique designs remain on the users’ PC, is the way to go.
“One of the problems with online is that your life lives on an anonymous cloud server. Even the owner probably doesn’t know where your information physically resides. That’s kind of a scary place for your skill set, career, and software package [to reside]. We’ve been sensitive to that concern. So we use [Dropbox] file sync, rather than [having users] occasionally download from a server. Everything you want lives on your computer, and we sync all the changes made in the database down to you almost immediately. It’s on your computer in your CAD tool’s format all the time, so you can still work if you go offline.”
Perhaps more daunting is simply convincing management at larger companies of the benefit of sharing their libraries. Friedman calls this a classic cost-benefit problem. “It’s a lot like accounting. If you ask upper management, they all swear by their CFOs. But if you said, “You no longer need to pay taxes or do reporting,” how many of them would keep this expensive expertise for those tasks? If one cost goes away, the resources devoted to it will free up. The Universal Parts Library frees up a lot of resources to do higher value-generating activity.”
Like many new cloud-based organizations, CircuitHub is relying on users to generate and share the content. And, like many organizations, it’s not charging for the right to use it. How can the company afford to do this?
It’s received seed funding from Google Ventures and various blue chip angel investors, including the inventors or founders of Gmail, Google SafeSearch, Reddit and others. But it appears the library is just the first spoke of a much bigger wheel. “Once a universal library like this exists, it allows many interesting things to happen in manufacturing and logistics. Those are the areas that we see developing,” Friedman says, without going into specifics.
The parts library is integrated with Altium, Cadence and Eagle. KiCAD and gEDA are in process, and Mentor and Zuken are also on CircuitHub’s roadmap. Integration work on the latter two will begin by the second quarter.
The company has four engineers among its five employees, meaning resources are at a premium. Yet, being an outsider and not tied to any specific tool has its luxuries. “We’ve taken a philosophical stand in aligning the product with the end-user,” says Friedman. “We aren’t owned by any one factory, distributor or manufacturer. We only care about making life easier for the engineer.
“One person should [prepare the footprint and symbology], someone else should check it, and it should be done. For everyone. In every tool. Forever.”
[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]
Mike Buetow is editor in chief of PCD&F (pcdandf.com); This email address is being protected from spambots. You need JavaScript enabled to view it..
I was updating DKN Research’s web page the other day, and received a failure notice when I tried to upload a few new pages. The alert indicated that my login or password was incorrect. No big deal, I probably entered in the wrong password.
