Ensuring signal integrity while compensating for curves.
You can tell when something isn’t as clear as it should be. The same questions come up time and again. You ask three experts and get three different answers.
Routing differential pairs can be like that. Why? Because “it depends” on exactly what signals those pairs are carrying and what kind of PCB you’re creating. Hopefully, I can answer some of those repeat questions, so you can concentrate on the hard stuff.
Fan-out and end routing. Let’s start at that differential driver on the left (). Imagine the TRUE () and COMPLEMENT () outputs are adjacent balls on a fine-pitch BGA, fanned-out to innerlayers. Whatever else you do, keep the trace lengths to fan-out vias equal, and keep the lengths after those vias equal until you start the parallel trace pattern. That parallel trace pattern is the coupled section because there’s electromagnetic coupling between the two sides.
Check with your EMS each time before sending your BoM.
Most of the electronics design world is by now aware we’re in a very serious period of component shortages. Ceramic capacitors seem to be the hardest hit, but other passives, as well as a variety of connectors and silicon parts, are also caught up in the shortage storm. Allocation and shortages hit every few years, but this one seems the worst in recent memory. It could be a problem until 2020, and the supply chain and world of components manufacturers will likely be a different animal coming out of it.
So, you might ask, isn’t that just a problem for high-volume producers? No, I would answer. It affects anyone, regardless of volume. The exact way it hits and what you can do about it may vary, but it has, or soon will, hit all of us.
A co-design solution for a wireless RF flip-chip design dilemma.
Solving for EMC issues within the layout is as important as completing DRCs.
When it comes to design rule checks for PCB designs, some should be performed that are just as important as spacing rules. Strict adherence to basic PCB design rule checks, such as track to track, track to via, via to via, pad to track etc. – though necessary to avoid short circuits – only scratch the surface when trying to identify potential design flaws. I often see PCB designs that are completed based on this premise and wonder what else could be hiding in the design?
DRC rules covering the verification of min and max length of routed critical signals like clicks and strobes, as well as skew differences in multi-bit buses, are as important as metal spacing rules. If the minimal skew is not achieved, the PCB design will be scrapped just as easily as if shorts resulted in burning holes in the PCB during power-up.