Exact adaptations of impedance are often not necessary. Instead, minimize impedance deviations.
In part 1 last month, we took a back-to-basics approach and discussed line impedance and its effects on signal integrity. Every electrical conductor comprises capacitance, an inductance, and a frequency-dependent ohmic resistance. With increasing frequencies, these electrical characteristics will influence and distort the signal.
Applying a transmission line model based on the telegrapher’s equations (as typically common in signal integrity considerations, except for when considering extremely high data rates, e.g., Serdes channels), one often-used general expression for the characteristic impedance of a lossy transmission line is:
Eq 1
where:
R = the resistance per unit length, considering the two conductors to be in a series
L = the inductance per unit length
G = the conductance of the dielectric per unit length
C = the capacitance per unit length
j = the imaginary unit, and
w = is the angular frequency.
As for the transmission line model, it was shown last month, but is worth showing again as a reminder (FIGURE 1).
Figure 1. Equivalent circuit of a transmission line. (Source: Wikipedia)
Although an infinite line is assumed, the characteristic impedance is independent of the length of the transmission line, as all quantities are per unit length. Hence, the electrical behavior of a digital signal is mainly determined by the geometry of the conductor. It is, therefore, possible to compute the above parameters and derive impedance and signal velocities from them. NB: The material characteristics of the insulator material (i.e., dielectrics) must also be known.
If a certain impedance is to be achieved for given trace dimensions (as specified by the PCB manufacturer), then by varying the dielectric height it is possible to achieve the required impedance value (FIGURE 2). Alternatively, the designer may also vary the dielectric material and thus influence the impedance by controlling the L and C characteristics. (For simplification, we are considering a lossless case; i.e., we neglect the frequency-dependent parameters R and G for the moment and assume there is no line resistance and no dielectric loss.)
Figure 2. Varying the dielectric properties can help achieve the desired trace impedance. (Zuken Field Solver GUI)
As the dielectric constant, ∑r, primarily influences the propagation of the E and H fields and the current flow through the conductor, it is obvious how important the surrounding medium (the dielectric material) is on the achieved impedance and the signal propagation. If there is no signal reference (ground or supply layer) in the immediate vicinity of the signal line, the signal return path is somewhat variable, and the impedance value of the transmission line can get very high. Worst case, it can get close to that of a single line in air (ZL = approximately 377W).
Due to the varying input resistances and different switching behavior of the ICs on a board, various impedance targets need to be matched when designing a large PCB. This makes it crucial to know the design constraints resulting from the layer stack structure (FIGURE 3) during the design process.
Figure 3. Sample layer-stack structure in 3-D. (Zuken CR-8000 Design Force)
Common engineering practice is to build a library of known layer-stacks with defined impedance configurations over time, so designers can relate to set values and not have to develop a new layer structure every time.
Visualizing the structure in 2-D or 3-D helps when designing higher complexity boards. In particularly challenging high-speed designs, it is common (but costly) practice to order impedance-controlled printed circuit boards, as all the design constraints and calculations were made during the design. Also note impedance-controlled PCBs are not produced using higher accuracy processes; the “control” implies the creation of test coupons for all possible impedance situations on all layers and enhanced testing whether the target is met or not. Proper impedance planning early in the design phase can help save the (typically) 25% premium for impedance-controlled boards.
Impedance calculations (especially when performed using web-based design tools) usually assume a rectangular cross-section of the finished circuit trace with a perfect current return path. However, the real cross-section is more likely to be a polygon approaching a trapezoidal shape, will sometimes cross gaps in the reference layer underneath (current return), and can vary widely from fabricator to fabricator.
This then raises the question whether the assumption of a rectangular cross-section for an impedance calculation is accurate enough, or will signal integrity be compromised by this imperfectly shaped cross-section? A field solver can account for the etching changing the trace geometry and can detect situations where the trace shows a so-called discontinuity.
As mentioned in part 1, to ensure a reflection-free signal, high-speed nets require impedance matching. This means the driver (output resistance), transmission line and receiver must show as little as possible (and ideally no) impedance difference values. In contrast, unmatched signals then show significant distortion (FIGURE 4). Routing may cause other issues, however. For instance, branches in topologies (FIGURE 5) can create a voltage divider and therefore produce a reflection point – despite a supposed ideal adaptation of the same resistance in all legs. (Perfect matching requires we use Kirchhoff’s law for resistance in parallel.)
Figure 4. Signal integrity – terminated signal matching the impedance (right) vs. unmatched (left).
Figure 5. A branched topology.
Do you need to be 100% on-target? Yes and no.
In digital electronics, data and information are often exchanged point-to-point between two components. It is mandatory that information is transmitted without being distorted or delayed. Signal integrity of critical signals must be ensured; hence, impedance control is the first step to do so. Deciding whether a signal still arrives with sufficient quality must be answered on the basis of the circuit characteristics and component specifications. In many cases, components can detect the switching information, even if the signal is slightly distorted. Alternatively, modern silicon can be programmed via hardware settings to significantly improve the signal quality at the receiver. If available, this option should always be used when working close to the limits of signal integrity budgets. Alternatives can be explored through signal integrity simulations.
To judge the effect on the signals, consider the two major reasons for impedance matching:
- Control the delay.
- Reduce reflections and attenuation.
In the fan-out area of high-pin BGAs, traces are often “necked-down” for routing space reasons between the BGA balls, which creates an impedance mismatch (i.e., a reflection situation). A typical 50Ω trace on an innerlayer has a propagation delay of about 6ns per m. If this transmission line is part of a differential pair and traverses (for instance) a BGA breakout region and has a ±30% impedance mismatch (i.e., 65Ω) over a length of 3cm, the signal transit time will be delayed by 6ps. This will create a small phase shift even at 3GHz. Not too much of a concern. The bigger issue is the risk of reflections.
Often, an exact adaptation of the impedance is not possible (and often unnecessary). Smaller mismatches are often still acceptable, as the proper logical switching of the signals is ensured by semiconductor switching tolerances.
However, no general design rule should be inferred from this. In such cases, it is more important to minimize the deviations of the impedances – and of course to be aware of the consequences. SI simulation tools will reveal their virtual prototyping power in such situations.
An example of the real-life impact of matched impedance is shown in FIGURE 6, where the switching behavior of a DDR3 data signal (point-to-point, the receiver only) is shown and where the memory vendor demanded an impedance value of 50Ω. During final verification of the PCB, the designer controlled all traces of the DDR3 interface, considering all possible manufacturing tolerances. (20% was stated by the board manufacturer.) When reaching the upper tolerance boundary of 60Ω, proper switching could not be ensured (a serious ring-back below the threshold is visible, yielding a timing error), whereas closer to the lower boundary (between 42 and 45Ω) signal behavior is best. This shows the strength of concurrent simulation as part of the design process and the benefits of conducting investigations on the virtual prototype.
Figure 6. DDR3 data signal with 60Ω (magenta) and 42Ω (green).
Conclusion
For cost-effective development of high-speed PCBs, know not only the different options of impedance-controlled design but also define the necessary and achievable tolerances.
A proven approach is to constrain upfront, design to target impedances, and optimize the PCB. The effects of an impedance mismatch must be known and understood. Simulation tools and virtual prototyping are keys to success. In addition, close collaboration with the PCB manufacturer – during the early stages of the project – is highly recommended. Indeed, the CAM departments of the PCB manufacturer can often provide proper indications to solve all impedance-related design questions. However, designers are advised not to hand over the control of impedance issues to external parties.
Ralf Bruening is product manager/senior consultant high-speed design solutions at Zuken (zuken.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. He will speak at PCB West in September at the Santa Clara (CA) Convention Center.
