2007 Issues

WLPs may be the answer to the widening gap between device cost and packaging cost.

Read more: R&D Needs for Packaging

Filled via-in-pad processes are a way to achieve an intermediate density increase for a minimal additional cost.

Read more: The Implementation of Via-in-Pad Interconnects to Increase PCB Circuit Density

Via fill for via-in-pad designs improves manufacturability from board fab through assembly.

Read more: Copper Via Fill – A Solution for HDI Via-in-Pad
Peter Bigelow Read more: Tainted Toys

The economic model for the optoelectronic interconnect favors high data rate transmission over moderate to long distances, limiting applications to high-end telecommunication systems.

Read more: Optoelectronic Substrates – Will it Happen?

Choose library tools that store component and land pattern data in a generic format that can be used with any CAD tool.

Read more: Building and Maintaining CAD Libraries

Page 5 of 21