2011 Issues

Thoughts on the analytical equipment, setup – and personnel.

The majority of surface analysis I use is for troubleshooting, but it is also a critical tool in new product development. We use perhaps two dozen in research and development over the course of a few weeks. The range is quite significant, from x-ray fluorescence (XRF) to understand a metal-plated thickness to much more sophisticated methods, such as Auger for elemental identification.

Knowing the appropriate method to use becomes the greatest challenge. How many times have you submitted a sample for scanning electron microscopy (SEM) and electron dispersion spectroscopy (EDS) that resulted in not finding what you hypothesized or even giving a direction forward?

This month, we offer insight into understanding how the analysis method can be adjusted to gather more valuable information. To discuss all techniques would be beyond our scope, so I will highlight a few and hope to offer some clarity.

XRF is a tool used multiple times a day in circuit board fabrication houses. Each first article is measured by XRF to confirm proper metal-plated thickness. XRFs need to be calibrated daily. This is important to measurement accuracy. Some may not realize that XRF units need application programs to be set up for each substrate being plated. You may think that if you are measuring ENIG on a printed circuit board or a ceramic substrate, you can use the same program. That is not the case. During program setup, the substrate is used; largely different substrates will require different application programs. Using one application for all substrates will result in false thickness readings.

Phosphorus analysis in electroless nickel is difficult for many. I have found that digestion is the most accurate method for such analysis, although it takes a meticulous analyst, as there are many dilutions. Some use XRF or EDS for identification, all methods requiring a standard. XRF suppliers have specialized hardware and software for measuring phosphorus in the EN deposit; not all XRF units are the right equipment for this analysis. Some will give you a number based on the application setup, but this is not accurate. For EDS analysis, I suggest cross-sectioning the deposit and measuring through the section. It is more accurate than a top-down analysis.
Understand the capabilities and limitations of each surface analysis method. This becomes more detailed for more sophisticated techniques such as Auger, XPS and TOF-SIMS. Such methods may not be the best tool for troubleshooting defect panels, especially if the parts have been through an entire manufacturing process or worse, a PCB assembly that has traveled through manufacturing and assembly. You will find every piece of dirt or air contaminant that the board has encountered in its life.

I was recently asked to perform XPS analysis on a product that had been through assembly, product build and functional test to identify the elemental characteristics of the surface treatment. I cautioned the requestor about the instrument sensitivity, noting that using a tool after this much handling can give overwhelming data. Although hesitant, I agreed to move forward, anticipating what could be found. After multiple separate XPS analyses, for which I was distanced from the analyst, the data resulted in more questions than answers. A final set was run with abbreviated assembly and no functional testing. I had to lay out a significant amount of molecular information to a “new to this project” test facility. The final analysis resulted in conflicting information to the previous three, but made much more sense according to the chemical makeup of the coating. There were still pieces of the report not fully understood, but overall, it was a tedious, time-consuming road to understanding pieces of my puzzle were as hypothesized. The moral is that surface analysis on this level gets expensive very quickly, and consulting the experts first and laying all details out upfront is the key to success.

A beautiful display of this was presented at SMTA International this October. The experiment was a combination of mixed flowing gas to create creep corrosion and TOF-SIMS to identify the corrosion product. Some may think the creep corrosion product had been established years ago by Veale1 and confirmed later by Schueller2 and others. The presented material gave further insight into the materials that contribute to the initiation of the reaction. It really was an impressive body of work that will be valuable for the entire industry – well thought-out and executed. Money and resources well spent.

References

1. R. Veale, “Reliability of PCB Alternate Surface Finishes in Harsh Industrial Environments,” SMTAI, October 2005.
2. Randy Schueller, Ph.D., “Creep Corrosion on Lead-Free Printed Circuit Boards in High Sulfur Environments,” SMTAI, October 2007.

Lenora Toscano is final finish product manager at MacDermid (macdermid.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. Her column appears quarterly.

The typical production timeline can be abridged by starting 2G designs during 1G prototyping.

In business, timing is everything. When is the best time for an OEM product or industrial designer to collaborate with their flex manufacturer and assembler? The correct answer should be: “That involvement is an infinite loop that begins during a product’s conception and perpetuates during a product’s evolution.”

In my October column, I focused on how to use flex technology as an enabler to make devices thinner, smaller and lighter. Now, I would like to illustrate an ideal methodology for OEMs to work with the flex manufacturer and assembler to enable technological products that consumers desire.

From my experience, the best flex manufacturers and assemblers provide engineering support early in the product lifecycle, which is typically comprised of six phases:

Concept: When industrial designers determine the desired form factor, features and user experience/interface of their products. This is the architectural stage and flex can play an enabling role.
Design: When product designers complete the electronics and mechanical design to achieve the desired form factor.
Prototype: After the design is complete, the flex manufacturers and assemblers physically create a proof-of-concept product prototype.
Pre-production: Making adjustments to the design to achieve desired performance requirements. The OEM looks to its suppliers to analyze root cause and test when problems are encountered.
Production: Ramping to full production volumes, often very rapidly to match the short marketability of products.
Maturity: End of a product lifespan, when it is ready for next-generation product introduction.

The flex manufacturer and assembler plays an integral role in each of the phases of the product lifecycle. The best flex-product integration is coordinated during the initial stage, which usually results in designs that produce best-in-class devices. It is imperative for any OEM to have early supplier involvement (“ESI”) with its flex manufacturers and assemblers. ESI enables OEM design and supply-chain teams to collaborate with their counterparts during this critical period. ESI provides designers added flexibility with minimal design constraints to maximize 3D packaging solutions. The result is seamless, integrated, flexible – printed circuit assembly solutions that lead to devices that are thinner, smaller and lighter with faster time-to-market.

Despite the best ESI efforts during the NPI stage of prototype and pre-production, engineering changes may be needed to further optimize the design for the desired product performance. In response, flex manufacturers must provide best-in-class program management and streamlined communications to achieve the design that yields the best product. After the design is optimized, the flex manufacturer must have the ability to quickly ramp to volume production, as well as support demand flexibility.

Through the maturity phase of the product lifecycle, the OEM design and supply chain teams would benefit from collaboration with the flex manufacturers to repeat the ESI and NPI phase for subsequent generations of product conception. We call this the “Infinite Loop of Involvement,” and it offers the flexibility to begin the ESI and NPI phase for the subsequent generation of product conception, as soon as the prototype phase of first-generation product is complete.

‘It’s never too early.’ When it comes to involving flex manufacturers and assemblers, one can never get engaged too early. In my experience, the most impressive packaging solutions have come from industrial, product and flex designers co-designing during product conception. That is the necessity of ESI. It is beneficial to proactively think how to use flex to help design thinner, lighter, and smaller products, instead of using flex as an afterthought for a potential fix. Typically, it takes 6 to 9 months to get to production volumes, but with this methodology, OEMs can shorten the process and bring products to market sooner.
It is not enough to just start early. A flex manufacturer should be involved in every phase of a new product’s lifecycle. There must be a culture of collaboration and unison between the OEM design team, the OEM supply chain, and the flex manufacturer and assembler. Once OEMs go through this process and move to a newer product, the loop begins anew. This perpetual cooperation leads to even more advanced, compact and cost-efficient products, and that is a tremendous plus for everyone.

Jay Desai is director of marketing at MFLEX (mflex.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

Suggestions for reducing channel-to-channel crosstalk.

At least four significant problems contribute to eye collapse and an increased bit error rate in high-speed serial links. Our previous two columns addressed how reflections and losses affect ISI, collapse of the eye, increased deterministic jitter and higher bit error rates. This month we look at how channel-to-channel crosstalk contributes to ISI and collapse of the eye.

Crosstalk from one channel to another can range from as high as 20% in some cases to as low as 0.01% in other cases. And just how much is too much, of course, depends on the received signal strength and how much noise margin is needed at the receiver. In an extreme case, the received signal may be as low as -30 dB from the transmitted signal and still acceptable. If a signal-to-noise ratio of at least 10 dB is desired, then the crosstalk should be less than -40 dB. This is less than 1%.

This is the basis of a simple rule of thumb. Unless you have an extreme channel, the channel-to-channel crosstalk should be kept below -40 dB. If it is ever larger than -40 dB, it may be important to perform analysis to see how much you can tolerate in your specific design.

One reason crosstalk discussions in the literature are so confusing is that so many design factors influence the magnitude of crosstalk. One could easily imagine a situation when it is a killer problem and other cases when it is trivial. It all depends on the specific design conditions and the criterion of how much is too much.
For example, consider a very bad, pathological situation, as illustrated in Figure 1. Two differential channels are routed in long lines in FR-4, but isolated from each other. However, there is a connector or package with 2" of trace in microstrip. Although it is designed as a 100Ω differential impedance, all four signal lines are tightly coupled with a spacing equal to their line width. This occurs very often in flex connector strips.

With a rise time of 25 psec, typical of a high-end PCIe gen II part, and a coupled length of 2", the FEXT would be about 20%. In this pathological
configuration, the far-end noise is generated close to the aggressor TX, so the rise time is the shortest, and the FEXT noise travels to the victim RX very close to the connector, so it suffers little attenuation.

The poor victim RX is at the end of a long, lossy interconnect, so the received signal is attenuated. If the two channels are asynchronous, the noise on the victim line is uncorrelated with the received bit, so the noise will spread uniformly over the entire unit interval.

This 20% FEXT noise, spread over the unit interval, can completely close a marginally acceptable eye, as in Figure 1. In some cases, channel-to-channel crosstalk can ruin your day, and it can arise in board traces, via stacks, connectors, packages and cables.



What can you do to reduce crosstalk to an acceptable level? Table 1 contains some suggestions. But, remember, you have to do your own analysis.

Dr. Eric Bogatin is a signal integrity evangelist with Bogatin Enterprises (beTheSignal.com), a LeCroy Co.; This email address is being protected from spambots. You need JavaScript enabled to view it..

When solder mask isn’t a viable via capping solution, there’s still hope.

Pad parts change and so do vias. Our standard policy is that open vias in pads are bad. We from time to time recommend ways to plug them. Generally, you have several options, such as capping the top or bottom of the via with solder mask. However, with vias in the pads of really small parts, those solder mask options will probably not work. Solder mask generally isn’t put down with enough precision to cover holes on tiny pads, and further, the solder mask would probably mess with the clearance, especially with very small QFNs. Immersion silver finishes may develop corrosion in sealed vias.

Figure 1 is an example of a small QFP with open vias in the pads. Those are some small vias.



If solder mask isn’t going to work, what will? Filling and plating over them, that’s what. You really have only two choices: fill and plate, or live with a bunch of voids under the part and solder slopped on the bottom side of the printed circuit board.

Figure 2 shows two illustrations representing the issue. In the top half of the image, the vias represented have copper plugs and are plated over by the board fabricator. As with all parts of this sort, there may still be tiny voids. IPC and the manufacturer have guidelines on the maximum allowable voiding. On the bottom, see what happens with the vias left open. Two problems: big voids and solder on the underside of the PCB.



Certainly there are some applications where this doesn’t matter. That’s why there is a second choice: “Live with a bunch of voids and slopped solder.” If you can’t live with voids and solder slop, you have to bite the bullet and pay extra for a PCB with filled vias. Board fabricators that do this have a variety of materials to use, including copper, electrically conductive epoxy and thermal conductive epoxy. Let your board fabricator know what your thermal requirements are, and they can help you choose the right fill material.

Ed.: Read Duane’s blog each week at circuitsassembly.com/blog/.

Duane Benson is marketing manager at Screaming Circuits (screamingcircuits.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. His column appears bimonthly.

A Formula for Rebuilding America’s Manufacturing Base and Competitive Electronics Manufacturing Industry

There’s a lot of discussion and speculation today about what’s wrong with the US economy, and what to do about it. It is generally agreed that part of the problem is that America’s manufacturing jobs have been outsourced to cheap labor markets overseas, and that reviving manufacturing in the US, with a healthy export trade, is part of the solution. How to achieve this, though, is the subject of much debate. With price pressure from these foreign markets making American goods less than competitive, how could we succeed?

In the electronics manufacturing industry, a truly global market, US-based manufacturers are in a quandary. The once-robust American electronics manufacturing and assembly industry has been gutted; most consumer electronics are assembled and manufactured in Asia. For example, cellular or wireless phone electronic components are produced almost exclusively in factories in China, Taiwan, Vietnam, and others. But it isn’t merely inexpensive or cheap consumer technology being produced there, but in fact highly complex and sophisticated electronics. This is actually an exception of sorts; generally we assume that high-volume, cheap consumer item manufacture is outsourced, while the lower-volume, more complex or difficult products are produced here. That’s not the case with electronics.
Our company, EI, is a printed circuit board fabricator based in the Chicago area. At one time, there was a robust PCB fab industry here in the US, much of it located in Southern California. But now, US-based PC fabricators are less numerous, in large part due to price pressure from overseas and pressure from environmental regulations and compliance requirements. The nature of our industry is such that it involves metals, chemistries, plating baths, and the generation of waste that must be properly treated or disposed of, something that is unfortunately not as much of an issue in countries where such regulations are lax or nonexistent. Compliance, though necessary, is still one factor that impacts cost, which in turn affects price competitiveness with PCBs produced overseas.

In terms of the US manufacturing industry as a whole, there is a way to turn things around. A good example to follow – not easy, but one that has worked – is the model that Germany has developed, sometimes referred to as the “BMW Model.” It must be working; in August of last year, The Observer’s Ruth Sunderland called the bounce-back of German manufacturing “… a testament to a business culture that has respect for manufacturing, and where exporters such as BMW or Bosch do not rely on a cheap currency to sell goods abroad but on the excellence of their products.” Sunderland calls Germany’s so-called Mittelstand – its small and medium-sized firms – “the backbone of the German economy,” adding they have “proved their durability and resilience.”1

And it’s more than that. Germany is a country where the revival of manufacturing is increasingly successful, and as a result they have brought unemployment down sharply to its lowest point in 20 years. Part of the secret has been to keep high-tech, high-capacity manufacturing at home, which keeps quality engineers in the country; they stay because these high-level jobs earn top wages. This keeps the brain trust at home, where it builds products considered the best in quality on the world market. Germany has invested in its people, and works constantly to support technological advancement and keep it in the country. To achieve this, it has continually invested in such things as training and internships, with the goal of keeping skills and knowledge within the country. It also forged successful cooperative associations with universities and educational institutions. The teamwork between government, industry, and institutions of training and higher education was a formula for success in terms of investing in people and providing the tools needed to fill the positions required by demanding technology.

It has been frequently said that America's best industry is producing Ph.Ds and highly educated people, but the problem is that once they have completed their education, they leave. We're losing our brain trust, because the people we educate, often from countries such as China, take that knowledge and return to their homelands, using their new skills to enhance the competitiveness of their domestic industries and economies against the US. In many instances they will help found companies that compete directly with US-based companies where they completed their internships or worked for a year or more!

High-technology, high-end manufacturing jobs pay well and attract the best candidates. They don’t need to be jobs at massive global corporations; in fact, some of the most innovative, forward-thinking, and prosperous companies are the American equivalent of Germany’s Mittelstand: small or mid-sized, established firms that invest in development and innovation. We need to invest in people – knowledge and training – and orient our efforts more toward those industries that demand a high level of knowledge and competence. Currently, we use only 22% of our total economic capacity here in the US for manufacturing; we are primarily a service sector economy. We can’t grow the US economy based solely on service. The German model is a bit different, where about 30% of the economy is industry and 70% is in the service sector. Remarkably, this is only about a 10 percentage point disparity, but in practice it constitutes a world of difference. Judging by the German model, if we shift only 10 percentage points of our resource capacity into manufacturing, perhaps a little more, we can go a long way to turning around the economy within a decade or two. Remember that economic growth is based on the GDP. The GDP in turn is based on earnings. High tech jobs require greater skills and training, and as a consequence, those jobs command better rates of pay. This contributes to boosting the GDP.

American industry has an ace in the hole, so to speak, that can help this turnaround, and also serves as an argument against outsourcing, and that is US infrastructure, manufacturing and transportation. Many people considering outsourcing don’t realize all the costs involved in sending work overseas. More than merely the costs of shipping, there are costs associated with lost time and risk factors that only become apparent once the process has begun. Developments in US infrastructure, begun during the Eisenhower years, have made the US the most cost-effective and reliable place to manufacture and deliver product. The logistics system within this country’s infrastructure is very efficient. Transportation in the US is still more efficient and cost-effective than anywhere else in the world. The lower risk factor associated with shipping goods within the US is a major cost consideration and incentive for manufacturing here.

Earlier we mentioned how high-volume, inexpensive consumer products for many industries are outsourced for manufacture in China, for example, while many high-reliability products continue to be manufactured here – in many cases. Yet, in the printed circuit board and electronics sector, this formula has been turned on its head. More complex printed circuit boards are being made overseas and shipped here for assembly, while low-tech circuitry, the type of technology that is been around for 20 years and more, is being produced here in the United States – the country that invented PCB technology! In fact, the majority of complex printed circuit boards assembled in the US are fabricated in Taiwan and China. The recipe for success for American electronics is to reverse this trend, so that the low-tech boards are being produced overseas, and the highly complex circuit assemblies and boards are being manufactured and fabricated here in America. It sounds like a simple solution, but it is not an easy one to implement; in PCB fab, for example, price pressure from overseas is high and margins are slim. It will take better machines, better technology, and more skilled engineers to boost the capability – not capacity – of electronics manufacturers here. That’s investment – and where is it to come from? If a US PCB fabricator can invest in greater capability; e.g., smaller features, lines, and connections on PCBs, to compete with overseas suppliers, we can resume advancing technology here and compete globally, sinking money into innovation and technology development.

Banks and finance institutions will need to provide needed financial support, such as low-interest loans, so they can invest in new equipment and move up to the next level of development. But I suggest this would take five or six years minimum. We know the recipe, but we don't quite know how to get there. We need a roadmap, and the roadmap begins with some sort of financial support to promote development in the circuit board industry, so that we can bring higher technology manufacturing back to the US to support growth and jobs. If these PCB manufacturers can expand their capabilities, the growth will follow and high-tech American products will be sold competitively in the world market.

There is a ripple-effect benefit as well. Electronics contract manufacturers and assemblers, also known as EMS providers, will grow too, and be more competitive, because they will have more local sources for boards for more complex products. The ripple effect will be felt across many associated industries, and have a direct benefit on the national economy. Too many US-based EMS companies buy their bare boards from overseas because fabricators in the US do not offer many products or even the capacity or capability to provide them.

We should focus on doing what we need to make our economy more lean, more efficient, more productive, and more complex, with a greater range and diversity of manufacturing. This will begin to reverse the tide of outsourcing and thereby grow the national economy while we enhance the prospects for our own businesses.

References
1. Ruth Sunderland, “German Business Culture Should Be a Model for Our Own,” The Observer, Aug. 14, 2010.

Pratish Patel is president and CEO of Electronic Interconnect (EI).

Putting these two under one roof provides OEMs greater assurances the end-product is successfully tested and avoids unforeseen problems.

PCB layout and test are inextricably intertwined. Some contract manufacturers maintain an in-house staff of layout designers, as well as assembly/test engineers. In such cases, the layout engineer delays creating all the necessary test points to avoid hindering routing. But once they finish critical routing and bus routing, an initial routing analysis and preliminary test points to achieve, say 50 or 60% coverage, they have the benefit of consulting with in-house test engineering to determine the right strategy to increase test coverage for the product.

OEMs that fail to take advantage of this basic and important practice when mapping out their system designs and manufacturing incur the greatest potential for extra costs, wasted time, and latent field failures. Consider the OEM that hands its printed circuit board design to a vendor located in one sector of the country. Then that OEM sends the electronic data (Gerber) to a fabricator at another geographic location. Afterward, the OEM purchases components and locates a third-party to perform assembly. Each stage – design, fab, and assembly – is distinctly separate from the others and, in effect, operates within its own confines with the OEM trying to successfully orchestrate the entire production cycle.

This process doesn’t make much business sense anymore, other than perhaps trying to save a few extra dollars. However, some OEMs still do this, especially those serving medical device and mil/aero markets, in which the slightest glitch can cause catastrophic consequences. Surprisingly, the consensus stance for doing it this way is simply, “We always have.”

What can go awry when opting for disparate operations? The OEM’s timeline, for starters. Consider the layout engineer at a selected PCB design house that performs only design and layout. Quite likely, they are involved with several design projects, each with specific completion dates. If that PCB layout engineer is behind schedule, causing a design to be late in delivering it to the fabricators, that triggers a domino effect with the fabricator experiencing unexpected delays, and delivery to the assembler (and market) gets compounded.

Murphy’s Law plays a role. Bad things do happen. The design and fabrication processes don’t quite jibe. The deliverables are not complete, or some critical information is missing, such as drill chart callouts or impedance control information. But the layout house argues that the problem rests with the fabricator. Finger-pointing continues until the problem is resolved, after much wasted time. Also, when using uncoordinated fabrication and assembly operations, the OEM fails to gain the benefits of highly coordinated resource expertise, which can be the difference between a product’s success and its failure.

Layout and Test Collaboration

Aside from these adverse issues, the crucial step of testing often gets short shrift when layout and assembly/test are vastly and geographically distant from one another. Ideally, a product gets the highest testing coverage possible – in the area of 85 to 95%. To accomplish those goals, having test and layout engineering under the same roof offers greater assurances they interact and jointly devise plans to successfully test the end-product. Experienced test engineers know all the nuances associated with in-house test systems. This is valuable knowledge that test engineers and technicians can pass to in-house layout engineering to be factored into designs.

It also helps when a seasoned layout engineer is familiar with flying probe and ICT test guidelines and limitations. For example, when a flying probe cannot reach a specific part of the board, that portion cannot be tested, thus reducing the test coverage. Then the layout engineer, keeping in mind those testing guidelines, can generate either more test points or use vias as test points to overcome that tester limitation (sidebar).

Testing is not jeopardized or shortchanged when PCB layout and test engineering maintain steady, orderly and productive collaboration. When a layout enters its final stages, the layout designer can transfer the CAD layout data to the testing department, where the testing access reporting mechanism can discern how much test coverage is actually available and on which kind of tester, keeping in mind the tester limitations. Here is where layout and test interaction pays handsome dividends. At this point, a series of mini conferences take place to discuss the steps the layout engineer needs to take to increase test coverage. Say, for example, test engineering determines a nearly completed design exhibits only 60% coverage. Since the PCB is still in the layout phase, the designer can use the new details and suggestions to add more test points or test vias, thus increasing testability access.

In this role, the PCB layout engineer must step out of their traditional design engineering routine and embrace a variety of test-related practices, procedures and disciplines, which need to be folded into the layout strategy at the placement, routing and finishing stages for a given board design. A classic example involves decoupling capacitors tied to an IC’s VCC or power pin. The smart PCB layout engineer ensures even distribution of those decoupling capacitors to help reduce noise. If the IC is not decoupled properly, locally generated noise ripples through the entire circuitry, creating jitter and ringing effects on the board. Those effects are later caught at the test stage, and the layout needs to be changed to reduce noise and jitter.

In another instance, the layout engineer must pay special attention when designing a high-speed bus that requires improved impedance and coupling control to satisfy the circuitry’s voltage and timing budgets. Special layout emphasis is critical for the bus design’s geometry and traces to develop proper test coupons. If not done properly, timing budgets will be off, and those mistakes will be caught at either debug or functional test stages, effectively too late for changes, short of re-spinning the board.

Also, in an RF application, signals generate parasitic coupling. The PCB layout engineer must implement ground shields or floods at the right locations in the layout to reduce parasitic coupling (Figure 1). Improving trace-to-trace impedance control is achieved by inserting ground shields between signal lines. This improves a uniform copper density across the entire board to ensure etch characteristics are equal to all signal lines. Again, if that’s not properly performed, test results send the layout back to the design for another go around.



Those are a few examples of what the savvy PCB layout engineer must know to successfully prepare a layout to achieve high-test coverage. Further, it’s important they fully understand the significance of such test procedures and characteristics as smoke test, gain and frequency response test, analog signature analysis (ASA), propagation velocity test, probing techniques, launch edge versus reflection edge, filtered TDR option, and others.

The smoke test is conducted to ascertain that data or signal aspects of the board are properly functioning. There are differences between a smoke test for digital and analog components. A smoke test provides some necessary assurances that system-under-test will not catastrophically fail. In other words, the circuit will not burn or systems will not crash. An example of the smoke test is the gain and frequency response testing. This involves measuring resistive points or loads between two different points to ensure they are balanced. The PCB layout engineer must understand this test because it helps prevent the circuit from burning, or at least avoids big mistakes from happening.

ASA monitors jitter, which occurs in digital ICs where the solid state jumps between two or three different points, thus causing instability. The experienced layout engineer will ensure a propagation delay between those two traces in order to make a stable state for doing ASA analysis, to control the jitter, and to ensure it’s within allowable parameters.

Propagation velocity testing involves propagation delay measurement and impedance measuring. Controlling impedance is relatively easy, and performing calculations and controlling a few factors to achieve impedance control is not difficult. But measuring propagation delay is considerably more difficult. Accuracy is extremely dependent on probing techniques dealing with connecting and terminating leads. Among the ones the PCB layout engineer needs to know about are handheld devices, SMA connectors, and controlled impedance micro probes, so they can factor in these test tools and considerations during layout.

As for launch edge versus reflection edge, the PCB layout engineer should have a firm understanding of this characteristic when doing high-speed designs. Last, filtered time domain reflects (TDR) option is used when excessive ringing occurs on a TDR response. Rise and fall edges must be aligned so they have zero time delay between rise and fall. Having this knowledge, the layout engineer is able to design the circuitry that is stable and has no jitters.

Sidebar:

Key ICT Guidelines

  • Don’t tie IC control lines directly to power or ground. Add pull-up or pull-down resistors. This permits the ICT to control these lines when required during IC testing.
  • Place test points away from BGA components to reduce BGA solder stress and board flex.
  • Have a test point for all electrical nodes, including unused IC pins. This allows detection of internal and external shorts.
  • To measure a low ohm resistor, two test points on each side of the component may be required to support 4-wire Kelvin resistance measuring.
  • Oscillator should be gated with logic circuit, allowing ICT to disable the clock signal as needed during IC testing.
  • Use boundary-scan-compliant devices when possible. This provides accessibility to the devices for boards with limited access test points. Also, chain multiple JTAG devices.
  • If possible, place test points for each node on one side of the board (secondary side preferred). This reduces the fixture and maintenance cost. Top-side probing is less accurate than bottom-side probing.

Zulki Khan is founder and president of NexLogic Technologies (nexlogic.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

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