IMAPS’ latest workshop showed just how far wafer-level packages have come.
Mobile phone shipments will account for more than 1.6 billion units this year, led by smartphones. The industry also is seeing a major shift to tablets for computing, communications, and many functions no one dreamed of a few years ago. With growth in these products and consumer preferences for thin, lightweight electronics comes demand for thin packages.
It was against this backdrop that IMAPS held its first Advanced Technology workshop on thin IC packaging in Santa Clara, CA, at the end of August. The following is a recap of the workshop.
Substrate warpage has proved challenging for packages, as substrate body sizes increase and thickness decreases. This has been especially critical in package-on-package (PoP). Three major IC package assembly subcontractors – Amkor, ASE and STATS ChipPAC – discussed PoP developments and issues, providing insight into the future of these packages. Shinko Electric provided details of its new embedded die technology, in which active die are embedded in the substrate of the bottom package in the PoP, enabling a lower profile package. ASE discussed its embedded chip process, in which the die is embedded in a buildup structure using laser drilling and metallization of microvias using an electrically conductive epoxy. Results from embedded die research programs at Georgia Tech were also presented. Amkor discussed the effects of package pitch and thickness reduction on board level reliability, as well as thermal fatigue issues for wafer level packages and flip chip CSPs. Hitachi Chemical introduced its new low CTE materials. Panasonic Electric Works discussed its substrate core material and new molding compounds. ASE provided details of its thin substrate. The 90µm thick a-S3, a prepreg glass fiber reinforced construction, is a single-sided substrate with al routing in one plane. Ajinomoto updated attendees with a preview of its next-generation buildup materials.
Recognizing the importance of materials in achieving thin packaging, several presentations focused on key technologies and breakthroughs in material development. With Amkor revealing further details of its copper pillar process, the importance of understanding the interaction between various materials could clearly be seen. In explaining that controlling mold shrinkage is critical, Panasonic Electric Works noted materials for next-generation flip chip CSPs with smaller gaps, adding that the molding materials would require smaller filler particles. Henkel presented developments in conductive die-attach film adhesives and wafer backside coating materials. Also introduced were new underfill materials from Henkel such as nonconductive paste (NCP) and wafer-applied underfill, both of which can be used with copper pillar bumps and TSV applications. Namics also presented its latest developments in underfill materials, discussing differences between NCP and non-conductive film (NCF). Namics also discussed capillary flow material deposition methods using jetting and vacuum.
The thinnest package wins. With the push for the lowest profile package, the industry has seen a strong increase in demand for WLPs. Almost every mobile phone and tablet computer has a handful of WLPs. With the growing die size and number of I/Os, a need emerged for a new technology to accommodate the requirement for a low profile. Thus was born the fan-out package. While a long list of companies has developed fan-out packages, Infineon’s eWLB technology has been adopted by ASE and STATS ChipPAC and is in high-volume production. A recent Samsung Galaxy smartphone contains eight WLPs, one of which uses Infineon’s eWLB technology. ASE and STATS ChipPAC detailed some of their latest developments in fan-out technology, including 3D versions.
3D and through silicon vias (TSVs) remain industry buzzwords and presentations from EVG. Optomec, Daetec and Amkor discussed various parts of the infrastructure. Silicon interposers were discussed, and a glimpse of future possibilities with glass interposers was provided by Georgia Tech.
With most of today’s stacked packaging still using wire bond, developments in wire bonding remain of great interest. Hesse and Knipps emphasized low loop wedge bonding for thin packages in one of the few wire-bond presentations.
If the presentations at the Think Thin workshop are any clue, the coming year will be filled with new developments in substrates, including coreless versions fabricated with new material sets, and new formulations of packaging materials such as mold compounds and underfills. Understanding interactions of new materials and the impact on reliability will require more attention to material science issues. Complexity in manufacturing and assembly appears to increase exponentially with package thickness reductions.
With every smartphone and media tablet specifying PoP for signal processing and memory architecture, resulting in over 11 million packages surface mount stacked per week, and trends to drive this package even thinner, almost every conference and meeting will provide a forum for additional discussion. Stay tuned for more from Amkor’s keynote at the SMTA International this month, which will focus on PoP trends, and technical sessions at ECTC in May in San Diego. Thin is in, and it may take a workout to meet industry goals.
E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. Her column appears bimonthly.
