Weighing in at some 1800 pages, the 2011 iNEMI Roadmap is the consortium’s most comprehensive to date. Editor in chief Mike Buetow spoke with iNEMI CEO Bill Bader last week about the roadmap’s latest points of emphasis, and about how an upsurge in membership is setting the pace for the future.

A design for quantitatively determining annular ring and breakout angle on PCB innerlayers.

If plated through-holes in multilayer printed circuit boards are not suitably registered, board reliability is threatened. Specifically, the annular ring on boards may be insufficient to ensure a good layer-to-layer bond and concomitant PTH integrity.

Useful data on PTH registration may be obtained using the test systems described by Paur in his two patents.^1,2 These systems provide more than a simple go/no-go measurement, but do not provide continuously variable data. The misregistration data are “binned,” as the system indicates misregistration within some interval, rather than being continuous. The systems also consume some space on a board panel and entail a slight increase in drilling time and tool use.

Acceptance standards IPC-6012 and IPC-6013 define three classes of PCB reliability, in order of increasing reliability requirements, denoted as Class 1, 2 and 3. Classes 1 and 2 permit some missing annular ring on internal layers, expressed as “breakout angle.” (Figure 2 demonstrates the concept of breakout angle. As of this writing, Class 1 boards may have internal annular ring with 180˚ breakout, and Class 2 boards may have internal annular ring with 90˚.)

The IPC the acceptance standards call for vertical microsections of coupons on PCBs, which do not allow measurement of breakout in internal annular ring. As Clifford3 demonstrated, even when vertical microsections meet Class 3 acceptability requirements, the PTHs themselves in reality may not meet breakout requirements. Horizontal microsections could reveal the actual breakout, but preparing such microsections is time-consuming in comparison to vertical ones. Another serious disadvantage of horizontal microsections is loss of a retainable record, as each section is destroyed as one proceeds into layers deeper and deeper in a PCB. Fabricators and users typically want microsection records and samples retained for some time after boards are made and shipped.

This unappealing situation led us to search for an exact way to measure internal annular ring breakout.

Geometry Review and Basis

Before going into the details of the new design, it may be worthwhile to review a tool from trigonometry, the Law of Cosines. We will use the law later in this article.

Many engineers and scientists are comfortable with use of the Law of Sines, which permits calculation of the length of all sides and magnitude of all angles in a triangle if the length of one side and magnitude of two angles are known. Per Figure 1, if the length of side A and angles b and c are known, the Law of Sines allows the length of sides B and C to be calculated:


Eq. 1

Less frequently seen is the Law of Cosines, which permits calculation of the length of all sides and magnitude of all angles in a triangle, if the length of two sides and magnitude of the angle between them are known.

Referring again to Figure 1, if the length of sides A and B and the angle c between them are known, the Law of Cosines allows the length of side C to be calculated:

Eq. 2

Refer now to Figure 2, representative of a hole drilled in a circular copper pad of a board. Using Figure 2, we show below that, knowing the displacement d of the center of the drilled hole of diameter r from the center of the circular pad of radius R, one can calculate the breakout angle 2τ by using the Law of Cosines.
The displacement d of the center of the drilled hole (red dot) and the center of the copper pad (blue dot) is, in terms of x and y,

Eq. 3



In the following, the notation (a,b) indicates the angle between a and b.
Using the Law of Cosines,


Eq. 4

Hence,

Eq. 5
and, with d calculated from ,



Eq. 6

From Figure 2, notice that


Eq. 7

So


Eq. 8

How does one determine x and y when the pad is on an internal layer? The next section has the answer. It also includes some comments on measurement of R and r. The latter two parameters are known, at least approximately from the design, but users of this new system can measure true values with relative ease.

Registration System and Measurements

Consider Figure 3, which shows the circular pad and drilled hole from Figure 2 and adds a chevron and a square pad to the right and left, respectively. The chevron and square pad are the two elements of the novel registration measurement structure. The chevron and square pad are formed at the same time, from the same material, and by the same process as the circular pad. Typically, the chevron and pads would be copper foil remaining after printing and developing of copper-clad laminate.

Notice that the length of the sides of the square pad is designed to be the same as the diameter of the circular pad, R. However, any layer-to-layer variations in printing, developing and etching the internal circular pads will also affect the square pad, so the true circular pad diameter can be determined by measuring the length of a side of the square pad.

The length of the chevron is equal to the diagonal of the square, Eq. 9.

E

Eq. 9

The diameter of the drilled hole, r, can be measured directly from the microsection, as the technique and equipment are designed to take the section through the center of the drilled hole.

Figure 4 contains the same elements as Figure 3, and adds the line S representing the plane of a vertical cross-section through the center of a hole drilled in a circuit board.

The user finds the value of x to be used in Eq. 3 by measuring the distance x’ between the observed center of the drilled hole and the observed center of the square, then subtracting from x’ the distance (already known as D from the design of the pads and their locations) between the center of the circular pad and the center of the square pad. Notice that the user makes one measurement, x’, to find the value of x from Eq. 10.


Eq. 10

The value of y to be used in Eq. 3 is found by measuring the distance y’ between the center of that portion of the chevron visible in the cross-section and the observed center of the square, then subtracting 2D from the measured distance y’. Notice, once again, that just one measurement, y’, is made to find the value of y from Eq. 11.


Eq. 11

The results from Eq. 10 and 11 allow calculation of breakout angle by utilizing the Law of Cosines. Note that, by definition of internal annular ring per IPC-T-50, the radius of the drilled hole, r, must be used, not the radius of the plated hole.

Advantages and Applications

This new method has some attractive features:

• Minimal space consumption on panel may often be incorporated into an A/B coupon.
• Precision of measurement of breakout angle and misregistration is limited by uncertainty in measurements of linear dimensions in coupons.
• Sample preparation takes place concurrent with standard microsection of multilayer panels.
• Allows preservation, as part of quality records, of breakout and misregistration information of all layers.
• If space consumption on a panel is extremely critical, the chevron could be incorporated as a “negative”; i.e, by removal of copper in the square pad.

A number of applications of the new method come to mind:

• Measurement of breakout angle for conformance to IPC Class 1 or 2 requirements, from vertical microsection.
• Variables data can be used in statistical process control of PCB lamination, for displacements of innerlayers.
• Variables data can be used in designed experiments for process optimization.
• Design rules can be formulated that incorporate statistics of drilling and lamination misregistrations to determine pad size on internal layers required to ensure a desired yield in fabrication.

References

1. Tom R. Paur, US Patent 4,894,606, System for Measuring Misregistration of Printed Circuit Board Layers, January 1990.
2. Tom R. Paur, US Patent 4,918,380, System for Measuring Misregistration, April 1990.
3. Tom Clifford, “Round the Clock,” Printed Circuit Design & Manufacture, June 2004.

Ed.: This article was first published at IPC Apex Expo in April 2011 and is republished here with the authors’ permission.

Russell Dudek is advanced technology manager and Louis Hart is quality assurance manager at Compunetics (compunetics.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

New technology drives new apps. Embedding components gives American manufacturing another chance to shine.

The electronics landscape is changing in ways unforeseen even a few years ago, and the interconnect, or printed circuit board (to use the old definition), is at the forefront of those changes. The underlying technology is changing in ways that few in the West now understand. With huge cost pressures and the shift of basic electronics manufacturing to Asia, these new manufacturing processes have fundamentally altered the topography in ways that present significant opportunities to designers and systems engineers, managers and marketers. These changes are also significant challenges to the relevance of the manufacturing and technology base in North America and Europe.

Consider the iPhone. Every day, new applications that go far beyond the original concept are being introduced. These include:

• Translation software – in over 25 languages – phonetically.
• Networking and situational awareness software.
• Personal identification software with network uplinks.
• Remote control software.

The iPhone has been on the market for just over 3-½ years. It is often forgotten that the software is driven by the capabilities of the hardware. In short, the new technology drives new apps.

Virtually all the components of the iPhone, however, are made outside the US, and the units are assembled in China and Taiwan. Apple has excellent designers and systems integrators whose expertise in the requirements for the technology is unsurpassed. But what actually makes it work – the underlying technology – is no longer understood in North America, except for a relatively few engineers. If we were called for any reason to manufacture these types of products in this country, we could not do so. We no longer have the manufacturing infrastructure.

Several key technologies make handheld and portable devices such powerful tools. The user interfaces are deeply intuitive. The massive miniature hard drives now hold up to 160 GB. The CPU board is a marvel of the most advanced circuit board and processor technology, and the circuit boards themselves are changing on a fundamental level.

High-density interconnect printed circuit boards are at the heart of today’s high-end technology. Signal paths are shortened; power consumption is reduced, and the package can be miniaturized. This technology was invented in the West, but today almost all the advances come from Japan. HDI is critical to miniaturization, ruggedization and high-level reliability, all nonnegotiable requirements for military electronics, as one example. Commercial and industrial applications are even greater. Unfortunately, HDI is hardly on the radar of the American manufacturing infrastructure.

Over $150 billion per year in finished products containing HDI, such as notebook computers, cellphones, GPS devices, consumer electronics, etc., are imported into North America every year. Annual demand for HDI substrates from assemblers in North America is well over $2 billion. The Japanese HDI industry is now producing $10 billion to $12 billion/year in revenue – roughly what the US and Japan each produced from all substrate types in 2000.1 Regrettably, the available capacity from US manufacturers is less than $200 million/year, including military and black box applications. This is a 50 to 60 times discrepancy. HDI has become an enabling technology. Once the three-dimensional topography of HDI becomes a focus, other things start happening.

Surface mount technology (SMT) began replacing plated through-hole technology in the early 1990s, and is now standard, even on most military and aerospace products. Improved product reliability and reduced costs contributed to mass conversion of most devices to SMT. While there are residual through-hole products on many printed circuit assemblies today, SMT constitutes over 90% of the market. SMT is now being gradually challenged by HDI-enabled embedded technology, in which both active and passive components are mounted inside the PCB.2,3,4 This is another game-changing technology. Very little if any work is being done on this in North America.

Embedded technology has several key advantages. First, the package can be made even smaller than it is today. In addition, because the package itself is rigid, reliability can be significantly enhanced in certain applications.4 To date, system-in-package (SiP) devices, including ASICs and memory, have been embedded successfully in commercial-grade substrates, making the interconnect an active device.

The security applications of this breakthrough technology alone should be of interest to the telecommunications, wireless, Internet and military communities. By embedding code and processors in the interconnect, the difficulty of decryption or of reverse-engineering can be enhanced exponentially. Signal paths are further reduced and signal integrity significantly enhanced. RF shielding can further enhance product security. In an age when commercial manufacturers typically have a six-month jump on the competition, embedded technology has the ability to provide significantly higher levels of technology security.

Within this milieu is another new technology that is rapidly changing the electronics landscape: MEMS (micro-electromechanical structures) and next, MESO-MEMS. Presently, these devices are used for gyroscopes and tracking systems in GPS devices; lab-on-a-chip applications; motion and distance detection systems in automotive applications, and even the Nintendo WII dance and exercise handsets.5 Again, very little of this technology is being manufactured in the West, and there is virtually no manufacturing exposure to the opportunities offered.

Optoelectronic circuit board technology is yet another field where the primary advances are now being made overseas. This will have significant ramifications in high-speed signal transmission, security, and many other applications.

The interconnect is changing from a passive to an active component. It is shrinking and becoming both more reliable and complex. It has become the nexus of the next-generation of electronic devices. While software development in North America is unparalleled, it must be matched with a deep and intimate understanding of the hardware and its capabilities and limitations.

The common thread running through all this is that the North American scientific, engineering and manufacturing base has lost touch with these fundamental electronics advances and the ability to develop, commercialize and utilize them successfully. This has profound ramifications for our industrial base. Where do the new products come from? Where do the startups that later become industrial giants obtain their technology?

A number of years ago, with the outsourcing/offshoring phenomenon, the desire to simplify and commodify acquisition processes, reduce costs and use commercially available, off-the-shelf technology, the US government and first-tier manufacturers deemphasized their involvement in the underlying technologies, setting manufacturing standards and even R&D. Today, we are faced with the results of those decisions.

The US’s infrastructure and economy are faced with many challenges of the post-recession and post-industrial economies. Our national welfare, defense and technology leadership are being challenged not by opposing powers or growing foreign economies, but rather by our inattention to the details.

References

1. IPC World PCB Market Report and Laminate Market Report for the Year 2000, February 2002.
2. Jim D. Raby, “Embedded Active Components for High-Reliability Products,” CIRCUITS ASSEMBLY, February 2008.
3. Tuomas Waris, Tanja Karila, Arni Kujala and Pekka Hildén, “Embedded Discrete Passive Components in PCBs using IMB Technology,” CARTS Europe, October 2008.
4. Noboru Fujimaki, Kiyoshi Koike, Kazuhiro Takami, Sigeyuki Ogata and Hiroshi Iinaga, “Development of Printed Circuit Board Technology Embedding Active and Passive Devices for e-Function Module,” Oki Technical Review, issue 216, vol. 77, no. 1, April 2010.
5. Arnaud Grivo, “Industrial PCB Development Using Embedded Passive and Active Discrete Chips Focused on Process and DfR,” IPC Apex, April 2010.

Matthew Holzmann is president of Christopher Associates (christopherweb.net); This email address is being protected from spambots. You need JavaScript enabled to view it..

A case study of a major defense OEM shows how even a good prevention program can be immensely improved.

The following Class 0 (see definition below) case studies illustrate the complexity and customization required to successfully produce products utilizing these ultra-sensitive devices. They also form the basis of a third-party qualification for Class 0 manufacturing operations by the ESD Journal.

It should be noted the term Class 0 has not been defined for manufacturing applications by any industry standard. We have found that manufacturing failure rates escalate exponentially for devices with ESD withstand voltages below 250V for either HBM or CDM. MM is intentionally omitted from this definition, since it is largely redundant to HBM. It is also vitally important the manufacturing process has a well-defined trigger for risk assessments of these ultra-sensitive components. These risk assessments involve verification of manufacturing process capability, as well as for any risks that may be passed on to customers. In some instances, risk assessments have resulted in the redesign of components to improve the ESD performance. Thus, we propose to define a Class 0 area for ESD manufacturing as one that includes components that have withstand voltages below 250V for either HBM or CDM.

It has become clear that customized manufacturing requirements for Class 0 products are essential. It is unlikely that any standards body will be able to develop a cookbook process in the foreseeable future. The variables are far too great for standardization. Hence the ESD Journal has developed a Seal of Approval.

The ESD Journal (esdjournal.com) Class 0 ESD Journal Seal of Approval for customized manufacturing operations dealing with these ultra-sensitive devices is based on peer review of application-appropriate customization for Class 0. It must be clearly demonstrated that the petitioning company has sufficient advanced technical expertise, as well as documented Class 0 procedures, yield success and exceptional compliance to procedure.

Two companies have achieved this level of recognition: Harold Datanetics Ltd., China, for its Class 0 Tape Head product manufacturing and BAE Systems in the US for Class 0 Manufacturing Excellence. BAE has also completed a requalification. (Additional companies are working diligently for the same recognition.)

Case study 1: Production stoppage. This Class 0 case study took place during ramp-up of a billion-dollar product line and at a time when advanced auditing techniques such as ESD event detection and current probe measurements were not being practiced. The production line was virtually shut down due to high failure rates. Severe yield losses coincided with the introduction of an N-type metal oxide semiconductor (NMOS) device with an ESD withstand voltage of 20V for both HBM and CDM. Major problems were encountered during device fabrication and printed circuit board assembly.

These low thresholds were the result of the lack of protection circuitry on the high-speed pins of the device. The designers presumed any such circuitry would prevent the device from performing its intended function. They ultimately were able to redesign the device and attain 1000V withstand voltages without compromising system performance. However, it was not in time to avert the following production crisis.

PCB assembly failure rates (Figure 1) were fluctuating between 10 and 30%, and some lots were 100% defective. Production was at a virtual standstill. The cost implications of continued failure were very high and were jeopardizing the entire product line. A detailed failure analysis investigation revealed that virtually all the failures were ESD-induced.

A technical assessment of the manufacturing line was undertaken, and an action plan compiled based on conventional wisdom at the time. Because of the extreme seriousness of this situation, the weekly reports were channeled to high-level executives in the company.

Initially, many extraordinary handling precautions were instituted, such as whole room ionization, bench ionizers, ESD garments, ESD chairs, constant wrist monitors, daily compliance verification, etc. Even with nearly flawless compliance to procedure, yields continued to fluctuate dramatically.

This problem was resolved with the introduction of a customized dissipative shunt referred to as a “top hat” (Figure 2). This shunt consisted of molded static dissipative foam precisely contoured to contact each lead of the device while on the circuit board. The top hat was placed on top of the NMOS device immediately after it had been assembled to the PCB. This resulted in the leads of the device being electrically connected through the static dissipative foam and static potential differences minimized.

The board was then processed normally through the rest of the assembly line until it reached final test, when the top hat had to be removed. This simple addition of a shunt to the device dramatically improved yields and resulted in failure rates of less than 2%.

The simplicity of this solution is particularly striking in contrast to more common alternatives that proved unsuccessful and costly. The extraordinary measures of using a multitude of standard precautions proved to be overkill and ineffective. The solution described here introduces a simple shunt into a set of existing procedures. The incremental cost was merely $1,000 for a set of top hats. The savings realized on the production line reached $6.2 million per year for this one device on this one line and enabled a billion-dollar product line to ship on time.

Another benefit derived was the impact on the design community. Asked to justify a withstand voltage of 20V for the NMOS device involved in the project, designers responded by redesigning the device and raising the level of sensitivity to 750V HBM and CDM, a remarkable accomplishment. Some system–level design changes were made to accommodate the new protection circuitry and maintain system performance.

This case study makes clear that ultrasensitive devices pose a significant threat to production lines and may result in lost production and lost sales. The financial implications are particularly unattractive when the cost of lost sales is added to the cost of lost materials.

As a direct result of the experience outlined in this case study, minimum design requirements were modified and a new set of handling requirements for Class 0 established. It was apparent that a cookbook approach to establishing handling criteria for ultrasensitive devices would not work. For example, it is likely some of the automated equipment used in the assembly process was causing the problem. Clearly, extraordinary controls such as room ionization could not solve the problem. Adding a shunt was not only necessary, but sufficient to protect the device at great economic benefit. In addition, the manufacturing line was able to continue to operate as usual and with minimal disruption.

In conclusion, a number of valuable lessons derived from this experience have led to today’s advanced approaches for Class 0 sensitivities. First, design transfer or new product introduction checklists must include ESD sensitivities, followed by risk assessments for devices below 250V or redesign of the product to eliminate these ultra-sensitive components. Also apparent: Customized solutions are essential for cost-effective mitigation of ESD failures. Advanced auditing techniques available today such as ESD event detection and current probe analysis enable scientific determination of optimal controls and countermeasures. The final ingredient is technical expertise to conduct advanced measurements and to develop application-appropriate remedies. These lessons learned helped to create a foundation for the following case study, as well as the creation of the ESD Journal Class 0 Seal of Approval.

Case study 2: BAE Systems. This case study began during new product introductions, when ESD failures were detected with failure analysis. BAE’s Nashua, NH, site had good ANSI/ESD S20.20 controls in place. However, even one failure would be too many for this high-reliability application. So, prior to ramping up production, BAE decided to bring in external expertise to prevent any production or reliability issues.

The approach started with a baseline technical assessment, followed by customized reengineering of each critical operation, the use of quality tracking metrics and advanced technical training. The detailed process changes involved application-appropriate customization.

The baseline technical assessment is a detailed analysis of each operation, looking at HBM compliance and alignment with ANSI/ESD S20.20. This is followed by advanced auditing techniques that include a variety of ESD event detectors and high-bandwidth current probes. More traditional measurement techniques such as electrostatic voltages can be helpful, but at times insufficient to detect subtle sources of losses. Event detection and current probe measurements have become essential tools for Class 0 applications. They enable systematic modification of each manufacturing operation to be either ESD discharge event free or to exhibit events far smaller than the current failure threshold. 

A multi-day workshop was conducted to elevate the users’ understanding of CDM and the technically advanced measurement techniques. Ultimately, the user must be able to fully understand Class 0 mitigation and measurement techniques. This training is reinforced with ongoing technical support for a full year to ensure the level of understanding required to achieve the Class 0 Seal of Approval.

Throughout this process, ESD Quality Metrics, including our novel Yield Risk Benchmarking methodology and meaningful quality metrics, are used to track the improvements. This enables management to set measurable goals and objectives and to efficiently monitor progress.

The benchmarking method is an accurate means of quantifying the performance of an ESD program, and there is a direct correlation to personnel compliance with ESD procedures. It has been successfully applied to hundreds of ESD programs.

The analysis of the strengths and weaknesses of BAE’s ESD program, as well as the progress over 18 months, is reflected in Figures 3 and 4. These indexes were derived from the novel methodology and were used as a guide for improvement. Virtually all elements now reach 90% or higher. BAE’s Yield Risk Benchmarking score started at 53% and ultimately reached 94%, and its process has not experienced a single ESD failure over a three-year period since implementing Class 0 controls.

Auditing, New Product Introduction and Class 0 Readiness showed sharp improvement. Auditing is one of the more critical elements of program management, and often improvement is essential to mitigate ESD losses. Data derived from auditing can be effective in the early identification and prioritization of process deviations. These data can also be used to effectively leverage limited resources for better Class 0 compliance.

Figures 5 and 6 track improvements. Figure 5 is the novel EPM Yield Risk Benchmarking and is a reflection of the ESD Quality System improvements. The blue line is the roadmap projected at the outset, and the red line is the actual performance that was validated each month. Figure 6 is the closure timeline for the action items in the associated technical assessment. Both trend tracking metrics followed the roadmaps closely, with impressive final scores of 93.6% and 96.6%. Figure 7 illustrates the remarkable improvement relative to the electronics and defense manufacturing industries.

Conclusions

Challenges presented by Class 0 ESD sensitivities are considerable and invariably require customization of mitigation techniques. The strategy employed proved highly effective. ESD failures were virtually eliminated, and the ESD team became competent and prepared for next-generation, sensitive Class 0 devices.

Elements of a good program include the following:

• Exceptional program administration, which includes verification of the ESD performance of incoming new product designs.
• Quality metrics with tracking scores of over 90% in each category. If you cannot measure an ESD manufacturing process, you do not have a functional process! With the process outlined here, Class 0 products may be successfully produced at very high yields.
• CDM and HBM countermeasures to be executed with rigorous compliance verification and virtually flawless adherence to procedure to avoid quality or reliability excursions.
• A deep understanding of the ESD technology and Class 0 mitigation techniques, best learned through intense initial training with ongoing reinforcement over a year or more.
• CDM mitigation techniques that include both methods: minimizing voltages on the product and controlling the surface resistance of materials that contact the conductive elements of the ESDS product.
• Customized reengineering of critical operations and strategic application of dissipative materials and ionization.
• Advanced measurements such as ESD event detectors and current probes.

Ted Dangelmayer is president and CEO of Dangelmayer Associates LLC (dangelmayer.com); This email address is being protected from spambots. You need JavaScript enabled to view it..