The National Institute for Occupational Safety and Health (NIOSH) received a confidential employee request for a Health Hazard Evaluation (HHE) at an electronics manufacturer specializing in printed circuit board fabrication, assembly, and testing for different end-user applications (sidebar). At the time of our evaluation, approximately 2,300 employees worked at the facility in either the medical section plant or the defense and aerospace section. Employees were primarily concerned about exposure to solder paste and fumes, as well as dust and noise. They reported coughs, burning eyes, nosebleeds, voice loss, headaches, sinus infections, bronchitis, and respiratory problems.
At the time of our evaluation, the medical section had four wave soldering lines and eight surface mount lines. Wave solder lines 1, 2, and 3 used Pb-free solder (96.5% tin), and wave solder line 4 used solder composed of 63% tin and 37% lead. The defense and aerospace section had five wave solder lines and six surface mount lines. It also had ruggedization, conformal coating and bonding operations, where the finished PCBs are fitted with additional structural supports and hand-brushed or sprayed with an acrylic copolymer to provide increased environmental and mechanical protection. Spraying during conformal coating was conducted in a ventilated, open-face, bench-top spray booth. Employees wore safety glasses and air-purifying, elastomeric, half facepiece respirators with organic vapor cartridges while spraying. At least once per shift, wave solder operators clean solder dross by using a ladle to remove dross floating on top of the molten solder (Figure 1). Residual molten solder inadvertently collected during this operation is separated with a sieve, and the remaining dross disposed of in a drum sealed with a lid. Employees are required to wear heat-resistant gloves over disposable nitrile gloves, a face shield, and an apron when performing dross cleaning. In addition to dross cleaning, employees periodically clean and maintain the wave solder machines. Finally, the facility has an auto insertion (AI) operation, which involves machine insertion of components onto a PCB by punching through it.
Assessment. During our first visit to the facility, we conducted confidential medical interviews with 40 employees, observed work processes and practices, collected general area air samples for volatile organic compounds (VOCs), and collected surface wipe samples for lead and tin. We also reviewed air sampling records, the respiratory protection program, injury and illness records, and material safety data sheets. After sharing our findings with employee and management representatives in an interim letter, we returned to the facility to collect personal breathing zone and general area air samples for lead and specific VOCs. We also measured noise levels at the AI stations, evaluated room acoustics near the air rotation units (ARUs), collected hand wipe samples to assess lead contamination on skin, and evaluated the effectiveness of the local exhaust hoods for the wave solder and surface mount machines (Figure 2).
Occupational exposure limits. NIOSH investigators use both mandatory (legally enforceable) and recommended occupational exposure limits (OELs) for chemical, physical, and biological agents as a guide for making recommendations. OELs have been developed by Federal agencies and safety and health organizations to prevent the occurrence of adverse health effects from workplace exposures. They suggest levels of exposure to which most employees may be exposed up to 10 hr. per day, 40 hr. per week for a working lifetime without experiencing adverse health effects. However, a small percentage of employees may still experience health effects due to personal susceptibility, a preexisting medical condition, and/or hypersensitivity (allergy). In addition, some hazardous substances may act in combination with other workplace exposures, the environment, or with medications or personal habits of the employee to produce health effects, even if occupational exposures are controlled at the level set by the exposure limit. Also, some substances can be absorbed by direct contact with the skin and mucous membranes in addition to being inhaled, which contributes to the individual’s overall exposure.
Results and Discussion
One of six personal breathing zone air samples for lead exceeded the Occupational Safety and Health Administration action limit (OSHA AL) of 30 micrograms per cubic meter (µg/m3) and was close to the OSHA permissible exposure limit of 50 µg/m3. This employee, a wave solder operator in the DAS, was cleaning the wave solder machines without wearing a respirator. The employee was exposed to an airborne lead concentration of 49 µg/m3. However, with this one exception, wave solder operators had lead exposures well below the OSHA AL.
Our surface sampling showed the presence of lead and tin on work surfaces in both sections of the plant. Currently, there are no OELs for surface metal contamination in occupational settings. We also sampled tables in two of the break rooms and found detectable levels of lead and tin in one of the break rooms. This suggests that workplace contamination is being tracked into the break rooms by employees’ footwear, clothing or hands, and that these areas should be kept cleaner.
Additionally, despite hand washing prior to sample collection, three of seven hand wipe samples tested positive for lead.
Full-shift noise exposures for the AI operators in the medical and defense and aerospace section were well below the NIOSH recommended exposure limit. Because telephone communication is not required in the production areas, and communication between employees is minimal, the louder noise levels experienced by employees with work stations near the ARUs were within the criteria specified by the balanced noise criteria (NCB) 55-70 curves. The NCB curves are a set of noise criteria for occupied interior spaces, devised to limit noise to levels at which speech can be reasonably understood. Refer to “Resources and Links” for more information on the NCB curves, as well as Appendix B of the HHE report (referenced in this section).
Our ventilation evaluation revealed that several local exhaust hoods were not effectively capturing process emissions. These included three hoods in the medical section and two hoods in the defense and aerospace section. This could have been due to local exhaust ventilation systems being imbalanced or improperly maintained. Air sampling results for specific VOCs indicated that employee exposures were well below all applicable OELs.
Although both the medical and defense and aerospace section share the main workspace and have similar tasks and equipment, the health concerns originated exclusively from employees in the medical section. Of the 40 medical section employees we interviewed, 23 did not report any work-related symptoms. The most commonly reported symptoms were upper respiratory, including runny nose, cough, and sinusitis; fatigue (frequently related to overtime work), and voice loss. However, these symptoms are also common in the general population, and we could not attribute them to the exposures documented.
Last, we found inconsistencies between the facility’s written respiratory protection program and employee practice. The written respiratory protection program required respirators to be worn when cleaning wave solder machines. However, it did not identify the appropriate type of respirator that should be worn for this task, and we did not observe employees wearing respirators when performing this activity. In addition, employees were voluntarily wearing respirators during spraying in the conformal coating area.
Recommendations
We made a number of recommendations to the facility to improve employee health and safety. Many of these recommendations may also apply to readers’ facilities:
Sidebar:
The Health Hazard Evaluation Program
Based on a federal law, NIOSH conducts Health Hazard Evaluations (HHE) to investigate possible workplace health hazards. Employees, employers or union representatives can ask our comprehensive team of experts to investigate their health and safety concerns by requesting an HHE. Our team contacts the requestor and discusses the problems and how to solve them. This may result in sending the requestor information, referring the requestor to a more appropriate agency, or making a site visit, which may include environmental sampling and medical testing. If we make a site visit, we prepare a report of our investigation that includes recommendations specific to the problems found, as well as general guidance for following good occupational health practices. HHE reports are available on the Internet (http://www.cdc.gov/niosh/hhe/).
Resources and Links
1. NIOSH HHE program information, cdc.gov/niosh/hhe/HHEprogram.html.
2. Link to this HHE report: cdc.gov/niosh/hhe/reports/pdfs/2007-0201-3086.pdf.
3. Code of Federal Regulations (CFR), 29 CFR 1910.95, US Government Printing Office, Office of the Federal Register.
4. L.L. Beranek, “Criteria for Noise and Vibration in Communities, Buildings, and Vehicles,” Noise and Vibration Control, Rev. ed. Cambridge, MA: Institute of Noise Control Engineering; 1988:554-623.
5. L.L. Beranek, “Balanced Noise Criterion (NCB) Curves,” J Acoust Soc Am., 1989; 86(2):650-664.
6. Acoustical Society of America, ANSI S12.2-1995, “Criteria for Evaluating Room Noise,” 1995.
7. Association of Occupational and Environmental Clinics (aoec.org).
8. American College of Occupational and Environmental Medicine (acoem.org).
Srinivas Durgam was an industrial hygienist at NIOSH (cdc.gov/niosh) during the time of this evaluation; This email address is being protected from spambots. You need JavaScript enabled to view it.. Chandran Achutan, Ph.D., is assistant professor at the University of Nebraska Medical Center (unmc.edu); This email address is being protected from spambots. You need JavaScript enabled to view it.. Carlos Aristeguieta, M.D., was a NIOSH medical officer during the time of this evaluation; This email address is being protected from spambots. You need JavaScript enabled to view it.. Maureen Niemeier is a freelance technical writer; This email address is being protected from spambots. You need JavaScript enabled to view it..
This month’s question: What is the typical industry standard for tolerance on the length and width of a flex circuit and also for stiffeners?
Answer: When it comes to dimensioning and tolerancing flexible circuits, less is usually better. Too many designers try to dimension a flex circuit as if it were a machined piece of steel. Keep in mind that the materials used to fabricate a flexible circuit are flexible. In addition to standard manufacturing tolerances, factor in the flexibility and dimension instability of the materials used in the construction.
A lot of factors cause flex circuit materials to grow or shrink before, during and after the circuit is constructed. Major physical factors that contribute to the dimensional instability of a flexible circuit are temperature and humidity. Like any material, polyimide film and acrylic/epoxy film adhesive (by far the most common building blocks for a flexible circuit) will expand when heated and shrink when cooled. While these changes may be small, over many inches of circuit length, they can add up. The other culprit is humidity. Flexible circuit materials are extremely hygroscopic and will not saturate until they have absorbed nearly 3% of their weight in moisture. As the circuits absorb moisture, they expand. The combination of temperature and humidity can cause a flex to change up to 0.001" per inch of length. So you can see that putting +/-0.005" on a 12"-long circuit can cause some problems.
Many years ago, I had a customer who ordered 18"-long flex circuits that had a tolerance of +/-0.005" on the overall length. Being young and inexperienced (I wasn’t always a Flexpert), I missed this, and we built and shipped the parts. About a week or so later, I received a call from the customer’s QA engineer telling me that the circuits were averaging 0.004" out of tolerance on the long side. I had the parts shipped back and when I measured them, they were actually averaging 0.001" under nominal. To make a long story short, these parts achieved frequent flyer status as they went back and forth between our facility and the customer’s. After about the third round, I realized what was happening. We were building the circuits in January in Minnesota (i.e., -20°F outside and less than 10% humidity inside). The customer, on the other hand, was in Tampa Bay, FL, where there is nearly always a fair amount of moisture in the air. All along, the parts had been growing and shrinking due to the wide variation of humidity levels between the two locations. I asked the customer’s QA engineer to give the circuits a low temp bake for an hour or so, and then measure them immediately after they cooled. Bingo! He got the same measurements as I was.
The bigger question is why had they specified +/-0.005" on a flex circuit 18" long? Did I mention that flexible circuits are flexible? I can’t imagine what application would need a tolerance that tight on a flex that long.
On the vast majority of drawings, I prefer to see just a few overall length and width dimensions that are reference, and let the CAD data drive the rest. If there is a dimension that is truly critical, by all means put in on the drawing and tolerance it accordingly. But realistically, since a flex circuit can bend, twist and flex, very few dimensions are truly critical. All dimensions on a drawing will have to be verified, which will add cost to the circuit. The designer needs to evaluate all dimensions that they put on the drawing and ask themselves if that dimension is going to add value, or just add cost.
So to answer the original question: Length and width of FPC would be +/-0.010" plus 0.001"/inch of length. This is the tightest that I would ever agree to, and I would prefer +/-0.020" plus 0.001"/inch.
Length and width of stiffeners. Since stiffeners are machined and constructed from a much more dimensionally stable material, they can hold tighter tolerances. But since you are putting them on a part that cannot support tight tolerances, are tight tolerances on a stiffener really necessary? They usually are not. For most normal-sized stiffeners, +/-0.010" is usually safe.
Always keep in mind that you pay for every dimension on a drawing either directly by potentially causing lower manufacturer yields or indirectly by requiring the manufacturer to verify each dimension. When dimensioning a new design, ask yourself if all those dimensions are adding value. Are you getting your money’s worth?
Mark Finstad is a senior application engineer at Flexible Circuit Technologies (flexiblecircuit.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. He and co-“Flexpert” Mark Verbrugge from PICA Manufacturing Solutions (This email address is being protected from spambots. You need JavaScript enabled to view it.) welcome your questions.
Have you ever wished for a feature in your design tools, maybe even requested it from your EDA vendor, but never seem to get what you want? I hear that a lot from my customers, and I doubt I’m alone. Sometimes the requests are good ideas that everyone can use, and they make the development list. Sometimes the requests facilitate a custom flow or procedure that just isn’t appropriate for a shrink-wrapped product. Regardless of how the request is categorized, it always seems to take longer to implement than the customer would like, mainly because they’d really like it right now.
Contrast this situation with your iPhone, iPad, or Droid phone. Need some new functionality? Chances are someone has already thought about it and created an app for it. I am amazed at the abundance of apps out there for smartphones and pads. Need a scientific calculator app? It’s there. How about an alarm clock, a gas mileage manager, voice recorder, book reader, or even the Angry Birds game? They’re all available.
Wouldn’t it be nice if you could get those apps in your design tool? OK, maybe not, but I would bet you can think of a lot of more germane nice-to-haves. I had one customer ask for a feature to synchronize test point placement between their PCB and schematic. Another said it was too difficult to find specific parts or values in their library of designs, and couldn’t we make that easier? Yet another wanted to automatically add various visual cues relating to production status to their schematic. There’s a never-ending stream of wants and desires out there. Sounds like the perfect scenario for a healthy dose of apps.
As PCD&F reported earlier this year, Cadence got things started by adding an app store to its OrCAD Capture frontend tool. Remember those customer requests I just mentioned? We implemented them for the customer, and then made them more generic for the general population and released them as apps. Apparently this isn’t unique to us, as other VARs are doing the same thing, helping us to create the first app store for the PCB design community.
We showed the apps and the store at the recent PCB West trade show, and found that users were thrilled to see that they had a new way to get more capabilities that they need, and that they could pick and choose which ones to get. As excited as I am to get this kind of response, I was probably more excited to hear other users saying they had some ideas and wanted to know how they could create their own apps. Imagine that: PCB tool users creating solutions to solve their own problems and then adding them to the pool of apps available to everyone.
This is similar to the concept of open source in that the user community has the ability to continually improve the tools they use. However, with apps, the added capabilities plug into the tool rather than modifying its base, so these new features become available the moment they are finished, rather than at the next release of the base tool. Another difference is that apps are based on scripting languages that are simpler to learn and use than C++ or many of the other programming languages used to create PCB tools. The developer has access to the database, command structure, and menu structure, making it relatively easy to implement features. Finally, problematic apps don’t ruin the whole tool; they can simply be removed.
That brings up a vital part of an app community: separating the good apps from the bad. Anyone actively downloading apps on their handheld devices knows that there are a lot of duds out there. Some just plain don’t work as advertised. We’ve built in quality assurance measures to minimize this problem, but the truth is there will still be imperfect apps. The key to this problem is the familiar rating system. Users of the apps get to rate the apps. Good apps get good ratings, and bad apps get left behind. It can be harsh, but it’s necessary to let this Darwinian approach to apps weed out the undesirable ones.
Another nice use of apps is to integrate existing tools with the schematic or PCB editing tool. We’ve come to expect the ability to launch another tool from the same vendor, but wouldn’t it be nice to build bridges between different vendors’ tools, especially if that bridge includes built-in knowledge of design? Similarly, a company with internal tools can create a more effective flow by tying the tools together. These apps can plug in to different versions of the PCB tools and can be shared between different design teams or the community at large.
I can see the user community adding some real vibrancy to our industry. It’s not too hard to imagine many apps available, because we’ve seen this with smartphones and pads, but I can also see a pool of developers looking for good ideas to implement. Some in the community will implement what they need with the scripting language, but others will take their wants and desires to an app developer for much quicker results, conforming to their specific needs. In fact, I’ll sign up to host the first app developer request line. Send me your wants and desires, and we’ll get to work building an abundance of PCB design apps.
Manny Marcano is president and CEO of EMA Design Automation (ema-eda.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. His column runs regularly.
What are the guidelines for tin whiskers in electronics assemblies, and how are they prevented? Part of the question can be answered by the Jedec and GEIA standards that delineate acceptance requirements for tin whiskers (Figure 1) in commercial and military hardware. But none of the methods outlined by the standards guarantees total mitigation of whisker growth.
No single accepted theory explains the tin whisker growth mechanism. The leading theories postulate the growth mechanism is powered by a release of internal stress in the tin finish or by re-crystallization and abnormal growth in the tin grain structure.1 Since the growth mechanism is not fully understood, the required environmental stress tests used for qualification, such as thermal cycling and thermal aging, do not necessarily simulate tin whisker growth in an assembly. A linear growth rate for tin whiskers has not been observed during long-term studies of whisker growth. There is a latency period after the coating is applied during which tin whiskers do not grow, which can range from a period of days to years. Once a whisker starts growing, it will most likely grow at a constant linear rate, but not all whiskers on a particular finish will grow at the same rate. This unpredictable whisker growth rate, which leads to inaccurate acceleration models, makes qualification testing of high-reliability electronics assemblies a challenge.
Qualification tests. For tin whisker acceptance testing, the commercial electronics industry has used Jedec standard JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes. Due to the long service life (>10 years) required for high-reliability electronics assemblies used in the aerospace and defense (A&D) industry (Table 1, Class 3), JESD201 requirements are not adequate. While valuable as a process evaluation tool for data comparison, the environmental test conditions do not correspond with actual A&D service environments. Tin whisker testing in JESD201 focuses on humidity, thermal cycling (1,500 cycles maximum), and calendar aging for a maximum of only 4,000 hr. (5.5 months). The A&D environment includes vibration, shock, corrosion, and even probe marks in the surface finish left behind during troubleshooting. These environmental conditions induce stress on the thin tin finish, which promotes the growth of tin whiskers.
GEIA-STD-0005-2, Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems, is presently the adopted standard used to manage (but not eliminate) tin whisker risk. These mitigation methods include SnPb solder dipping of component leads, conductor spacing control, and conformal coating. Unfortunately, the current knowledge base does not include decades of experience to verify the success of these mitigation methods and their effect on system reliability.
Mitigation techniques. While pure tin and high tin content finishes are not recommended for Class 3 assemblies, the push to restrain A&D electronics costs has precipitated the use of COTS (commercial off-the-shelf) components whenever possible. Unfortunately, since pure tin finished devices are common and inexpensive, they have inadvertently made their way through A&D supply chains. Component manufacturers and distributors frequently use the lot number as the only discriminator to distinguish the Pb-free finish. Even reputable distributors have difficulty tracking lots of pure tin finished components versus the same component with an alternate finish.
As a first level of tin whisker mitigation, it is critical to screen for pure tin finished components at incoming receiving. Conformal coating, required for most military applications, is another whisker mitigation technique frequently used to help retard the effects of whisker growth. By isolating individual leads, the coating can prevent arcing due to whisker bridges. The more elastic coatings rely on elongation properties to prevent penetration. Other coatings rely on their hardness to restrain or redirect whiskers to grow back on themselves, preventing them from breaking through and potentially shorting. It must be reiterated that currently conformal coating is not a foolproof method to prevent whisker growth.
Various methods and materials are available for conformal coating. The following have been the most commonly used, with most having been qualified under IPC-CC-830. The coatings are listed in increasing order by their expected tin whisker mitigating value.
1. Acrylic: can be dipped or sprayed.
2. Silicone: can be dipped or sprayed.
3. Epoxy: can be dipped or sprayed.
4. Parylene: chemical vapor deposition.
5. Arathane 5750 (formerly Uralane 5750)2 Urethane: can be dipped or sprayed.
6. ALD-Cap3: high alumina ceramic applied using atomic layer deposition.
With research still pending, ALD-Cap high alumina conformal coating has shown encouraging signs as a reliable method for tin whisker mitigation.
References
1. Jay Brusse, Kim Jong, Michael Sampson and Henning Leidecker. “Basic Info on Tin Whiskers.” NASA Electronic Parts and Packaging (NEPP) Program, http://nepp.nasa.gov/whisker/background/index.htm.
2. Jay Brusse, Kim Jong, Michael Sampson and Henning Leidecker, “Characterize the Effectiveness of Arathane 5750 (formerly Known as Uralane 5750) Conformal Coat Material in Prohibiting Tin Whisker Formation and/or Tin Whisker Penetration.” NASA Electronic Parts and Packaging (NEPP) Program, http://nepp.nasa.gov/WHISKER/experiment/exp2/.
3. Ofer Sneh, “N04-058: ALD-Cap: Thin Film Encapsulating Coating for Hermetic Environmental Protection,” Navy SBIR Success Story, July 25, 2009. https://www.navysbirsearch.com/widgets/hyperlinking/successdetails.jsp?url=DocURL&id=90078.
4. The Lead-Free Electronics Manhattan Project – Phase I. Benchmarking and Best Practices, July 30, 2009. http://www.dodb2pcoe.org/LFEMP_book.pdf.
ACI Technologies Inc. (aciusa.org) is the National Center of Excellence in Electronics Manufacturing, specializing in manufacturing services, IPC standards and manufacturing training, failure analysis and other analytical services. This column appears monthly.
Mobile phone shipments will account for more than 1.6 billion units this year, led by smartphones. The industry also is seeing a major shift to tablets for computing, communications, and many functions no one dreamed of a few years ago. With growth in these products and consumer preferences for thin, lightweight electronics comes demand for thin packages.
It was against this backdrop that IMAPS held its first Advanced Technology workshop on thin IC packaging in Santa Clara, CA, at the end of August. The following is a recap of the workshop.
Substrate warpage has proved challenging for packages, as substrate body sizes increase and thickness decreases. This has been especially critical in package-on-package (PoP). Three major IC package assembly subcontractors – Amkor, ASE and STATS ChipPAC – discussed PoP developments and issues, providing insight into the future of these packages. Shinko Electric provided details of its new embedded die technology, in which active die are embedded in the substrate of the bottom package in the PoP, enabling a lower profile package. ASE discussed its embedded chip process, in which the die is embedded in a buildup structure using laser drilling and metallization of microvias using an electrically conductive epoxy. Results from embedded die research programs at Georgia Tech were also presented. Amkor discussed the effects of package pitch and thickness reduction on board level reliability, as well as thermal fatigue issues for wafer level packages and flip chip CSPs. Hitachi Chemical introduced its new low CTE materials. Panasonic Electric Works discussed its substrate core material and new molding compounds. ASE provided details of its thin substrate. The 90µm thick a-S3, a prepreg glass fiber reinforced construction, is a single-sided substrate with al routing in one plane. Ajinomoto updated attendees with a preview of its next-generation buildup materials.
Recognizing the importance of materials in achieving thin packaging, several presentations focused on key technologies and breakthroughs in material development. With Amkor revealing further details of its copper pillar process, the importance of understanding the interaction between various materials could clearly be seen. In explaining that controlling mold shrinkage is critical, Panasonic Electric Works noted materials for next-generation flip chip CSPs with smaller gaps, adding that the molding materials would require smaller filler particles. Henkel presented developments in conductive die-attach film adhesives and wafer backside coating materials. Also introduced were new underfill materials from Henkel such as nonconductive paste (NCP) and wafer-applied underfill, both of which can be used with copper pillar bumps and TSV applications. Namics also presented its latest developments in underfill materials, discussing differences between NCP and non-conductive film (NCF). Namics also discussed capillary flow material deposition methods using jetting and vacuum.
The thinnest package wins. With the push for the lowest profile package, the industry has seen a strong increase in demand for WLPs. Almost every mobile phone and tablet computer has a handful of WLPs. With the growing die size and number of I/Os, a need emerged for a new technology to accommodate the requirement for a low profile. Thus was born the fan-out package. While a long list of companies has developed fan-out packages, Infineon’s eWLB technology has been adopted by ASE and STATS ChipPAC and is in high-volume production. A recent Samsung Galaxy smartphone contains eight WLPs, one of which uses Infineon’s eWLB technology. ASE and STATS ChipPAC detailed some of their latest developments in fan-out technology, including 3D versions.
3D and through silicon vias (TSVs) remain industry buzzwords and presentations from EVG. Optomec, Daetec and Amkor discussed various parts of the infrastructure. Silicon interposers were discussed, and a glimpse of future possibilities with glass interposers was provided by Georgia Tech.
With most of today’s stacked packaging still using wire bond, developments in wire bonding remain of great interest. Hesse and Knipps emphasized low loop wedge bonding for thin packages in one of the few wire-bond presentations.
If the presentations at the Think Thin workshop are any clue, the coming year will be filled with new developments in substrates, including coreless versions fabricated with new material sets, and new formulations of packaging materials such as mold compounds and underfills. Understanding interactions of new materials and the impact on reliability will require more attention to material science issues. Complexity in manufacturing and assembly appears to increase exponentially with package thickness reductions.
With every smartphone and media tablet specifying PoP for signal processing and memory architecture, resulting in over 11 million packages surface mount stacked per week, and trends to drive this package even thinner, almost every conference and meeting will provide a forum for additional discussion. Stay tuned for more from Amkor’s keynote at the SMTA International this month, which will focus on PoP trends, and technical sessions at ECTC in May in San Diego. Thin is in, and it may take a workout to meet industry goals.
E. Jan Vardaman is president of TechSearch International (techsearchinc.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. Her column appears bimonthly.
Printed circuit boards for microwave circuits must meet a special set of requirements. They must support transmission of signals with the diminutive wavelengths of radio-frequency (RF) and microwave frequencies, and they must do so with minimal loss and stable, consistent performance. To best understand high-frequency PCBs, it helps to review the types of transmission lines and structures typically used in RF/microwave circuits and how PCB characteristics relate to electrical performance at higher frequencies.
The three most common transmission-line technologies used in microwave circuits are microstrip, coplanar and stripline circuits. Of the three, microstrip transmission lines are most often used in high-frequency PCBs, since they are relatively simple to fabricate and with fewer electrical variables to consider than the other two approaches. Figure 1 shows a simple drawing of a microstrip PCB. A microstrip consists of a conductive strip and a wider ground plane, separated by a dielectric layer.
Electromagnetic propagation in a microstrip circuit occurs by means of transverse-electromagnetic (TEM) plane waves. In an ideal microstrip circuit, signal energy propagates perpendicular to the electric (E) and magnetic (H) fields. In an actual microstrip circuit, because propagation also takes place in the dielectric material between the conductors, as well as in the air above the conductors, propagation occurs in a quasi-TEM mode.
There are four types of signal losses in a microstrip transmission line: conductor, dielectric, radiation, and leakage losses. Leakage losses usually are not a concern, due to the high volume resistivity (resistance) of PCB materials used for microwave circuits. At microwave frequencies, radiation losses tend to be more of an issue for microstrip circuits than for coplanar or stripline circuits. Dielectric losses are a function of the PCB substrate material; in terms of loss performance, different materials can be compared by a parameter known as dissipation factor. Lower values of dissipation factor signify laminates with lower dielectric losses. Conductor losses are not quite as simple to size up because they are linked to a number of different variables in a microstrip circuit.
Conductor losses are related to the way that current flows along a conductor. Known as “skin effect,” current will tend to flow closer to the surface of a conductor at higher frequencies. As frequency increases, the skin depth is less and a signal’s current flows along the conductor by using less of the conductor at higher frequencies. Most of the current density in a microstrip signal conductor is at the interface between the two copper planes and at the bottom corners of the conductor (Figure 2).
Skin depth, δ, can be calculated from the equality in Eq. 1:
δ = [1/(2πfµσ)]0.5 (Eq. 1)
where f is frequency, µ is the permeability of the conductor, and σ is the conductivity of the conductor, typically copper in an RF/microwave microstrip PCB. (The conductivity of copper is generally accepted to be about 5.8 x 107 S/m.) The parameter for permeability in Eq. 1 is actually a complex quantity given by µ = µ0µr, where µ0 is the permeability of free space and µr is a multiplier related to the type of metal used as the conductor. For copper, the value of µr is assumed to be about unity (1), although there are some exceptions, as well as issues related to different conductivity values.
For example, the surface roughness of the copper conductor, at a circuit’s copper-substrate interface, can impact the loss of a microstrip circuit. A rougher conductor surface suffers higher losses. Several methods have been developed to account for the copper roughness, and a simple model is the Morgan rule,1 which is a multiplier of the conductor losses (αc). Generalized conductor loss and the Morgan rule are given by Eqs. 2 and 3, respectively:
αc = 1/δ (Eq. 2)
αc + roughness = αc{1 + (2/π)[tan-1(∆/δ)2]} (Eq. 3)
where αc + roughness is the total conductor loss, including loss due to copper conductor roughness. Parameter ∆ in Eq. 3 represents the root-mean-square (RMS) surface roughness of the copper conductor. As with many models, the Morgan rule is limited at certain frequencies, and is typically more accurate at frequencies of less than 10GHz.
How do these models and relationships translate into actual PCB applications? In looking at Eq. 1, it is apparent that skin depth decreases with increasing frequency. In Eq. 2, as the skin depth, δ, decreases, the conductor loss, αc, will increase. Higher frequencies translate into higher conductor losses. As frequencies increase, the effects of copper conductor surface roughness also increase, to a point where Eq. 3 will reach a saturation point at its highest value.
To demonstrate the effects of copper conductor surface roughness, Figure 3 offers a comparison of the same dielectric substrate, but with two different levels of copper surface roughness. In both cases, microstrip transmission lines were fabricated on the PCBs. The PCB substrate with the rougher copper conductor surface is standard Rogers RO4350B laminate material, while the substrate with the smoother copper conductor surface is RO4350B LoPro. The curves for the two microstrip transmission lines in Figure 3 are also compared to a microstrip model2 using the Morgan rule, with good correlation at lower frequencies.
Different types of PCB conductor finish can also provide different results in terms of conductor losses at higher frequencies. For example, an electroless-nickel/immersion-gold (ENIG) plated finish is often used on copper conductors. As Figure 2 shows, most electric fields in a high-frequency microstrip transmission line lie between the copper layers, although a significant current density exists at the corners of the signal conductor. ENIG plating affects EM fields at a conductor’s edges and corners. At lower frequencies, current flows within the skin of the conductor and uses the copper. But at higher frequencies, where the skin depth is less, most of the current density is concentrated in the NiAu finish of an ENIG-plated conductor. This gold plating is typically very thin, 10 microinches or less, while the nickel layer is considerably thicker, typically 150 to 300 microinches.
Gold is slightly less conductive than copper and has no ferromagnetic properties (µr = 1), so it has relatively little impact on the conductor’s loss characteristics at higher frequencies. But nickel is much less conductive than copper (about one-third that of copper), and nickel also has strong ferromagnetic properties, with a high permeability value and with µr value of about 500. Lower conductivity will increase conductor loss. High µr value will decrease the skin depth (per Eq. 1) and keep the current density in the conductor within a narrow region of low-conductivity nickel. To minimize this effect, PCB suppliers typically use one of a number of different ENIG processes, often with a form of nickel alloy, to minimize unwanted ferromagnetic properties in conductors.
The manner in which copper is treated in the process of making a PCB’s copper foil can impact conductor losses. For example, when two PCBs with different copper types but with nearly identical conductor surface roughness profiles were evaluated, they were found to have very different loss responses. The copper with the inferior loss performance was found to have undergone a nickel allow treatment. In general, a conductor composed of ore treated with a ferromagnetic material will exhibit degraded conductor losses in microwave transmission lines.
Numerous PCB variables influence the impedance of a microstrip transmission line, such as laminate dielectric constant (known as Dk, εr, relative permittivity), thickness, copper weight, and control of circuit etching. For high-frequency applications, it is important that a PCB laminate have well-controlled Dk, as well as tightly controlled thickness, since variations in either will result in variations in transmission-line impedance.
A number of other factors can influence the impedance of a high-frequency PCB’s transmission lines. Dispersion, for example, is often overlooked. Dispersion is a microstrip transmission-line property in which the propagation characteristics are different at lower frequencies than at higher frequencies. Dispersion can also be a concern in PCB materials where the Dk value is considerably different at lower and higher frequencies. Dispersion typically plagues PCB laminates not nominally engineered for high-frequency applications, but is minimized in higher-quality PCB materials meant for high-frequency circuits. To demonstrate differences in dispersion characteristics for different materials, Figure 4 compares high-performance FR-4 substrate with RO4350B laminate, both with microstrip transmission lines fabricated on 0.020"-thick substrates.
Environmental conditions can also play a role in how well a PCB material maintains impedance, especially at higher frequencies. Many traditional PCB materials may not have been formulated for stable Dk performance in changing or hostile environments. All PCB materials are characterized by a parameter known as thermal coefficient of dielectric constant, or TCDk, in units of ppm/°C. This parameter describes how much the dielectric constant will change with changes in temperature. These changes in Dk will also change the impedance of the microstrip transmission lines, so lower values of TCDk (resulting in minimal effects on impedance) are preferred. For example, it is not unusual for standard FR-4 to exhibit a TCDk value of 200 ppm/°C or more. In contrast, many high-frequency PCB laminates are engineered to exhibit a TCDk value of 50 ppm/°C or less.
Humidity can also affect PCB performance. If a PCB material is prone to absorb moisture, the water content can impact loss performance and impedance stability. Many standard PCB laminates have moisture absorption values of 2% or more, which means in a humid environment, the laminate can absorb moisture readily, and the electrical properties change. Compared to PCB materials, the Dk of water is very high (about 70). In an environment with high humidity, excessive moisture absorption can raise a PCB material’s Dk and increase its dielectric loss. PCB materials formulated for high-frequency use typically exhibit low moisture absorption, with values of 0.2% or less.
Microstrip is probably the most popular high-frequency transmission-line technology, but coplanar transmission lines are also widely used in RF/microwave circuit designs. There are many different variants of coplanar transmission lines. The coplanar structure most often used in high-frequency circuits is known as coplanar waveguide (CPW) or specifically conductor-backed coplanar waveguide (CBCPW). Figure 5 presents a simple drawing of a CBCPW transmission line.
CBCPW transmission lines offer a number of benefits compared to microstrip, including much lower radiation losses and very low dispersion. CBCPW transmission lines can support extremely wide bandwidths, as well as a wide range of impedance values, for ease of matching to low-impedance devices such as microwave power transistors. The primary limitations of CBCPW transmission lines have to do with their inherently higher conductor losses compared to microstrip, and the need for forming plated through-hole (PTH) via holes for signal and ground connections between circuit layers.
Microstrip radiation losses can be significant above certain frequencies and/or with certain circuit geometries. At very high frequencies, radiation losses can dominate the performance of a microstrip circuit and negate the benefits of using conductors with smooth copper or laminate material with low dissipation factor. One way to avoid the high radiation losses of microstrip at high frequencies is through the use of CBCPW transmission lines. When properly designed, CBCPW transmission lines can support quasi-TEM wave propagation at very high frequencies, beyond the frequency limit of microstrip. This can be seen in the results of a study performed by Southwest Microwave, Inc. (southwestmicrowave.com) comparing different transmission-line structures at test frequencies through 50GHz (Figure 6). The “knee” in the loss curve for the microstrip structures shown in Figure 6 is where radiation losses become dominant. When properly designed, a coplanar transmission-line structure does not exhibit this frequency dependency.
Stripline is probably the most stable of the three main high-frequency transmission lines. Sometimes called flat coaxial transmission line, it features a signal layer sandwiched between top and bottom ground planes. In contrast to microstrip, stripline has numerous benefits, including no radiation losses and no dispersion. It can support true TEM wave propagation and is capable of extremely wideband frequency performance. With its double ground plane and buried signal structure, external electrical influences have little or no effect on stripline circuits.
There are also drawbacks to stripline transmission-line technology. Fabrication costs for stripline are higher than those for microstrip or CBCPW transmission-line structures. Stripline is also more limited to the range of possible impedance values, and signal losses in stripline are higher than for either microstrip or CPCPW circuits. Figure 7 shows a magnified cross-sectional view of a stripline structure.
Stripline transmission lines suffer higher loss compared to microstrip transmission lines because microstrip benefits from partial wave propagation through the air above the circuit; the dielectric losses of air are lower than those of the laminate materials surrounding the conductor layer in a stripline circuit. A stripline circuit structure will also use a narrower signal conductor for a given impedance, such as the 50Ω typically used in microwave circuits, than a microstrip circuit structure, and the narrower conductor will result in higher conductor losses compared to the wider conductor used in microstrip. Compared to microstrip, a stripline circuit will be affected more by the copper conductor surface because of the two ground return paths. A smooth copper conductor surface can provide performance benefits, whereas a rough copper conductor surface can contribute to higher conductor losses.
This brief comparison of three high-frequency transmission-line types has offered some insight into the PCB material characteristics that can affect high-frequency performance, such as conductor losses. By better understanding the benefits of circuit materials formulated for high-frequency applications, circuit designers can more readily achieve their final goals in terms of electrical performance at RF/microwave frequencies.
References
1. S. P. Morgan, “Effect of Surface Roughness on Eddy Current Losses at Microwave Frequencies,” Journal of Applied Physics, v. 20, 1949, p. 352.
2. MWI-2010 Impedance model (download at rogerscorp.com/acm). The microstrip model uses the Hammerstad and Jenson model: E. Hammerstad and O. Jenson, “Accurate models of microstrip computer aided design,” 1980 Microwave Theory & Techniques Symposium (MTT-S) International Symposium Digest, May 1980, pp. 407-409.
3. Bill Rosas, “Optimizing Test Boards for 50 GHz End Launch Connectors: Grounded Coplanar Launches and Through Lines on 30mil Rogers RO4350B with Comparison to Microstrip,” Southwest Microwave Inc., 2007.
John Coonrod is a market development engineer at Rogers Corp., Advanced Circuit Materials Division (rogers.com); This email address is being protected from spambots. You need JavaScript enabled to view it..