Smartlam 5200 automatic cut sheet laminator is designed for processing ultra-thin materials with the option of wet lamination in a high-volume production environment. Is designed around tacking system; is made of redesigned conveyors, centering unit and devices that allow handling of material in and out of the lamination rollers at the tacking point. Wet lamination system has a new design. Updated software offers greater flexibility in setting processing parameters. Lamination of substrates up to 12mm is possible.
EMSAT Viewer pairs EMSAT post-layout EMC and SI design rule checkers developed by IBM with a Pantheon EMSAT Viewer that displays each violation on the board in real-time. Includes tree view that mimics EMSATuser interface, along with descriptive error reporting. Tree view is interactive, allowing users to view a report on errors or click through each error to view the violation on the board. Violations are displayed using arrows and highlight objects. Viewed errors display in gray italics. Corrections can be made directly in Pantheon and exported back for analysis in EMSAT using the DSN output file. Checks for common violation types in a layout that lead to EMC or SI degradation. Rule types can be tailored to each design. Rule checking is accomplished by reading in .brd, .dsn, .hyp, .mcm, or .xml; critical objects in the layout are designated, such as I/O nets, power/ground nets, clock nets, and decoupling capacitors; then each of the EMSAT rules are run on the design, and errors are reported and stored in output files. Pantheon can use one of 35+ database translators in tandem with EMSAT viewer and EMSAT violation file.
SpiCalci simulation software calculates performance characteristics and parameters for switch mode power supply (SMPS) capacitors. Features enhanced part selection and includes nearly all new SMPS devices introduced by AVX over the past two years. Allows inputting of raw data and generates output information and graphs to aid in SMPS capacitor selection. Accepts inputs and selects a variety of raw data, including: part type, case size, voltage, dielectric, capacitance, tolerance, ambient temperature (°C), temperature rise (°C), and operating frequency (kHz) for catalog, military, and aerospace parts. Output data is provided in two categories: Specifications for this Design and Specifications Varying with Temperature. Is free of charge.
LIOELM TCL500 / TSU 500 series low dielectric materials are said to reduce transmission losses by using an original low dielectric resin. Contribute to the widening of printed-circuit traces or narrowing gaps between lines. TCL500 consists of 25 micron low dielectric adhesive layer and release film. TSU 500 consists of 12.5 micron photoimageable film, 25 micron low dielectric adhesive layer and release film. Copper adhesion strength is 10 n/cm, Dk is 2.55 @ 1 or 5GHz, and dissipation factor is 0.006 at 1GHz and 0.004 at 5GHz.
DDR Debug Toolkit, for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals, provides test, debug and analysis tools for the entire DDR design cycle. Read and Write bursts can be separated and eye diagrams for each can be displayed in real time, providing unique insight to system performance with a single push-button. Identifies root causes of problems with jitter analysis specifically designed for bursted DDR signals that conventional serial data tools cannot analyze. Includes a variety of built-in DDR-specific measurement parameters, enabling easy quantitative analysis of system performance. Performs DDR analysis simultaneously over four different measurement scenarios, improving DDR testing efficiency and providing faster results. Displays up to 10 eye diagrams simultaneously. Multi-measurement scenario analysis capability lends itself to optimization and tuning of system and device performance, while the built-in measurements provide characterization benchmarks for precompliance testing. For testing to JEDEC standards, analysis tools can be leveraged to perform margin testing and to troubleshoot failures which arise during compliance testing. Provides alternative to automated DDR compliance test packages for times when full compliance testing is not required.
Pulsonix 8.5 schematic capture and PCB layout tool features new Panel Editor enabling multi-board designs to be panelized for plotting, plus the addition of test coupons, fiducial markers, documentation and fabrication details. Offers IPC-2581 netlist export and Gerber X2 manufacturing outputs. Imports library formats from PCB Libraries, Accelerated Designs and SnapEDA. Library manager enhanced to allow drag-and-drop methodology from native ASCII files directly into the library. Adds cyclic design backups and security saves, cross probing of Star (Delta) Points, individual width and offsetting of cross hatching, additional DRC checks, import PCB component placement CSV format and multiple group selection for design reuse in Apply Layout pattern as well as multiple positional rearrangement optio
