Companies and research organizations worldwide have described the advantages of stacking chips vertically with through silicon vias to provide improved performance by delivering increased bandwidth, reduced latency, and lower power. The timing for mass production depends on the existence of an established infrastructure that includes the installation and qualification of high-volume 300 mm production lines, assembly and test capability and how the cost of the new technology compares with that of existing technologies.

Read more: Xilinx FPGA Plans Enable Infrastructure for 2.D TSV

SAN JOSE – Cadence reported third-quarter net income of $127 million, a big jump from last year when the EDA software vendor lost $14 million.

Read more: Cadence’s Q3 Revenue Up 10% YoY