How to specify, validate and monitor PCB backdrill requirements during NPI and production.
As PCB designs incorporate higher-speed signals, and reducing via stubs becomes critical to function, backdrilling is often treated as a simple requirement added to the fabrication drawing. Designers trust the PCB fabricator's process to meet their stub requirement, but validation of this critical requirement is often overlooked.
The backdrill note in the fabrication drawing can be perfectly clear, but the fabricator may still fail to meet the stub length requirement. This will not appear at bareboard electrical tests, and it may show up later as margin loss, intermittent high-speed failures or unexplained channel performance variation. The fabricator’s success in their backdrill operation depends on clear design requirements, stackup accuracy, layer registration, primary drill and backdrill registration and process repeatability. These factors can be validated in several ways: coupon inspection, first-article CT scan, time domain reflectometry (TDR) or destructive physical analysis (DPA).
Here are recommendations for high-speed backdrill requirements and validation methods to use with your PCB fabricator.
Specify the requirement. In my experience reviewing high-speed PCB designs for manufacturability, I have found inconsistencies in the way backdrill requirements are specified. I’ve seen long, detailed fabrication notes, backdrill tables with conflicting requirements or simply backdrill layers without any stub length tolerance specified. For the PCB fabricator to be successful, the fabrication drawing and data package must include the target backdrill stub length, tolerance, layer span and the must-not-cut (MNC) layer for each backdrill.
Listing the backdrill size is optional, since allowing the PCB fabricator to choose the backdrill drill bit size allows them to optimize the bit when compared to the primary drill size and surrounding copper features or anti-pads. Avoid using maximum backdrill depth as part of the acceptance requirements, as it may conflict with the stub length and MNC layer requirements once the fabricator models the stackup.
The electrical intent with backdrilling is to maintain residual stub length and avoid drill damage to the MNC layer. The fabricator will translate these requirements into their own drill depth targets. I also suggest referencing the applicable revision of IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, as part of the general PCB acceptance criteria since IPC-6012 includes microsectioning requirements for backdrilled holes.
An example of a backdrill requirement might look like this:
Table 1. Backdrill Requirements by Layer Span
Design factors that affect process capability. Stackup design affects the success of the backdrill operation. The backdrill operation must account for a laminated panel larger than the resulting PCB with tolerances for dielectric thickness, copper distribution, resin flow and primary drill registration. As the stub length tolerances decrease, the fabricator’s control of each of these tolerances matters. With a balanced single-lamination design, some advanced fabricators may be able to demonstrate very tight residual stub control, even as low as 4+/-2mils. But this target is quite difficult to meet if the stackup is unbalanced, the backdrill depth exceeds standard capability, or multiple laminations are involved.
Process artifacts like floating copper or copper stripes may appear in the backdrill section of the hole. See Figure 4 for an example of a copper stripe. These artifacts may cause the same issues as a residual stub over the target. Fabricators need to incorporate specialized processes to achieve such tight tolerances, such as layer mapping or drill mapping. Specialized equipment may map the thickness across a panel, measure the MNC layer depth after the primary drill, or electrically sense a target layer with features in a non-plated hole.
When determining the stub length target, don’t just choose the best stub length that the fabricator can achieve. Choose the stub length target based on the design speed. A rule of thumb for Intel Xeon reference platforms was that PCIe Gen 5 used 7+/-5mils, PCIe Gen 6 used 6+/-4mils, and PCIe Gen 7 would use 4+/-2mils. Keep the same requirement across a layer span for consistency in the fabricator’s process, so in a multi-lamination stackup, a through-hole may use a 7+/-5mils requirement while the sub-lamination blind vias may use a 4+/-2mils requirement.
Figure 1. Example of multilamination stackup showing separate backdrill requirements for through-hole and sub-lamination vias.
Validate the result. With the requirements set, the next challenge is validating that the fabricator has achieved the target. There are some steps a fabricator will take on their own to verify their process against the acceptance criteria. The fabricator may design coupons that reflect the backdrill area padstacks to physically measure a microsection for the backdrill stub. This coupon stub length should be correlated to the PCB design’s stub length by performing a DPA on a failed or sample board from the lot.
The fabricator may use automated x-ray inspection to verify registration between the primary and backdrill holes, with a CT scan for any nonconforming results or for first-article testing when available. I’ve seen newer equipment that uses TDR to identify via-stub reflections and correlate the response with residual stub length, but I have yet to see this used in production environments. Don’t expect that insertion loss coupons, such as delta-L, characterize backdrill stub length; specialized test coupons or probes are required for this type of testing.
Figure 2. Backdrill microsection showing nominal, over-drilled and under-drilled conditions.
Figure 3. TDR measurement showing backdrill stub reflection.
Figure 4. CT scan showing backdrill stripe.
Table 2. Backdrill Validation Tools, Applications and Limitations
What to ask the fabricator. How should the implementation of these process checks be monitored? The most important step is direct communication with the PCB fabricator. Design feedback should be requested on copper balancing within the stackup, where the backdrill stub is critical to function. A clear understanding should be established regarding the process controls the fabricator will implement to meet the specified requirement and whether any capacity limitations may affect production volumes.
During NPI, measured evidence should be provided that correlates coupon results to product DPA. At minimum, the data should include the measurement method, sample size, measured stub lengths, mean, range and variation relative to the specified tolerance. For high-risk designs, requirements should define whether a 3σ or Cpk-based process capability target is necessary.
Backdrill stub lengths should be spot-checked on any material or failure analysis performed by the PCBA contract manufacturer. Product functionality should be monitored during NPI testing for issues that may be attributed to PCB stub lengths. Changes to the design or stackup that would require process revalidation should be identified in advance.
Finally, the need for a sampling plan during high-volume manufacturing should be determined based on the fabricator's demonstrated process capability.
Treat Backdrill as a Controlled Process
Backdrilling is not just a fabrication requirement; it is also a manufacturing process to be validated. A good backdrill fabrication note defines the stub length target, tolerance, and must-not-cut layer, and gives the fabricator the right information to control their process. A good NPI plan will verify that the fabricator’s process meets the design requirement. Work with the PCB fabricator to implement the right design requirements, design feedback, process controls and sampling plans.
Joe Clark is senior principal NPI engineer at SambaNova with 10+ years of experience across OpenAI, Intel and Lockheed Martin.
