WASHINGTON -- An International Trade Commission panel tasked with resolving a two-year patent battle pitting Rambus against Nvidia and several other big-name tech companies will delay ruling for two more months.

Read more: ITC Delays Rambus Patent Ruling

SYDNEY – Altium has added Aldec's FPGA simulation capabilities to its Designer software.

Read more: Altium Designer Now Has Aldec FPGA Simulation

SAN JOSE – Cadence has joined IBM to create high-performance integration-optimized IP to help deliver leading-edge designs, while reducing the risk and time associated with integrating complex SoC designs.

Read more: Cadence, IBM to Develop Joint DDR IP

DARMSTADT, GERMANY -- To address customer demand for integrated layout and 3D full wave analysis, Computer Simulation Technology has undertaken a major collaborative project to enable layout engineers to stay within the Cadence environment while performing a full wave 3D extraction and EM analysis in the background.

Read more: CST Announces Simplified Workflow for Full 3D Simulation in Cadence SiP Flow