Companies and research organizations worldwide have described the advantages of stacking chips vertically with through silicon vias to provide improved performance by delivering increased bandwidth, reduced latency, and lower power. The timing for mass production depends on the existence of an established infrastructure that includes the installation and qualification of high-volume 300 mm production lines, assembly and test capability and how the cost of the new technology compares with that of existing technologies.

Many companies have been considering the use of a silicon interposer to provide a 2.5D solution. While the concept of a silicon interposer is not new, many companies have expressed concerns that the supply chain for silicon interposers was not sufficiently mature to support its adoption. The announcement last week from Xilinx, in partnership with TSMC and Amkor, provides the first example of a commercial path to 2.5D with the use of a silicon interposer supplied by TSMC. The promise from TSMC of a stable supply of silicon interposers provides a critical part of the infrastructure. This development could delay the need for full 3D TSV in many applications.

Xilinx announced its 28 nm Virtex-7 LX2000T using a “Stacked Silicon Interposer” as the world’s first multi-die FPGA providing more than 3.5 times the logic capacity of the largest current-generation Xilinx 40 nm FPGA with serial transceivers and 2.8 times the logic capacity of the largest competing 28 nm FPGA with serial transceivers. The device is made possible by using four FPGA slices fabricated by TSMC that sit in a side-by-side configuration connected with copper micro bumps to a passive silicon interposer. The interposer, fabricated by TSMC uses 65 nm generation silicon technology and has four conventional metal layers to connect each FPGA slice. The passive silicon interposer with through silicon via is mounted using flip-chip interconnect to a flip-chip organic substrate supplied by Ibiden. The structure provides a lower latency and a high yield solution. Engineering samples are planned for mid 2011.

Xilinx has been researching 3D TSV for five years and benefited from collaboration with leading industry organizations including IMEC, SEMATECH, and SEMI, as well as equipment manufacturers, fabs and OSATs. A robust supply chain enabled by a close partnership among Xilinx for FPGA, interposer and package design plus final package test, TSMC for 28 nm FPGA and interposer fabrication, Amkor for micro bumping, die singulation, chip-on-chip attach, and assembly, and Ibiden for package substrate made the product possible.

E. Jan Vardaman is president of TechSearch International and a CIRCUITS ASSEMBLY contributing editor; This email address is being protected from spambots. You need JavaScript enabled to view it.

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