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Details: Written by Staff; Category: Design News; Published: 04 June 2008

SHENZHEN, CHINA – Valor computerized Systems has signed an agreement establishing a technological partnership with the Guilin University of Electronic Technology (GUET). Valor and GUET will cooperate to encourage technical talent and develop and promote new technology within the industry.

“Valor has been playing an important role in the development of the electronics manufacturing industry. We fully recognize the significance and value of this cooperation,” said Professor Tianlong Gu, VP of GUET.

Under the terms of the agreement, Valor will provide GUET with software, including DFM, SMT programming, optimization, program conversion and process engineering etc., and GUET will bring Valor software into its courses in undergraduate and postgraduate studies programs. In addition, a training room for electronic manufacturing software applications will be established for vocational training purposes.

“We are fully aware of the importance of this technological cooperation between GUET and Valor. As one of the few selective universities who have SMT courses in China, GUET’s contribution to the development of China electronics manufacturing industry, as well as the cultivation of professionals are well recognized,” said KH Ong, president, Valor Far East.

The Guilin University of Electronic Technology features electronics and information technology as its main disciplines and is reportedly one of the largest campuses in China, with more than 17,000 students studying at the university.

Details: Written by Staff; Category: Design News; Published: 04 June 2008

CARLSBAD, CA - Altium has introduced a software upgrade for the Altium Designer product that allows electronics designers to fit boards into enclosures in 3D, eliminating trial-and-error iterations.

Building on Altium’s 3D PCB visualization software, the company uses the STEP 3D file format as a mechanism to link to external STEP models from within Altium Designer to bring a casing model into the PCB design environment.

The upgrade allows designers to create a board shape from the case model, do mechanical fit and clearance checking, and update board design or component choice placement for fit and conformance to physical design constraints. If the mechanical designer changes the case design, the new design can be updated within Altium program. The board design can also be used by the program as a STEP model for use by the mechanical designer.

Nick Martin, CEO of Altium, said, “Electronics design companies are looking for new ways to innovate and sustain differentiation, and companies are recognizing the benefits of a unified design solution. The new ECAD-MCAD collaboration capabilities of Altium Designer demonstrate…a unified approach to product development.”

Details: Written by Staff; Category: Design News; Published: 04 June 2008

LONDON - Premier EDA Solutions has signed up as an exhibitor at National Electronics Week (NEW) to be held at London’s Earls Court from June 17 to 19.

“National Electronics Week is an ideal forum for us to showcase our customer success. Today’s industry takes no prisoners and, in the UK, the ability to innovate is essential for longevity,” said Premier Managing Director, Phil Mayo.

NEW Event Director Claire Jeffreys adds, “We have so much to be proud of here in the UK, not least a vibrant electronics industry that is driven by a world-class spirit of innovation. NEW is dedicated to delivering a total industry event with an unprecedented scope of coverage.”

Details: Written by Staff; Category: Design News; Published: 03 June 2008

SAN JOSE, CA and WILSONVILLE, OR - Cadence Design Systems and Mentor Graphics have announced the publication of a book on Open Verification Methodology (OVM).

Step-by-Step Functional Verification with SystemVerilog and OVM is written by Dr. Sasan Iman.

The book provides a claimed guide and reference for adopting a functional verification methodology, learning the SystemVerilog language, and using the OVM library to build a verification environment for a realistic design example. The book reportedly contains more than 500 pages of original technical content.

"Dr. Iman brings together all the essential elements to understand the use and application of the OVM," said Dennis Brophy, director at Mentor Graphics. "This book has everything design and verification engineers would want to know to apply the OVM to their most pressing challenges."

"This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of this book and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers." said Ted Vucurevich, CTO at Cadence.

The publication is available at either of the following sites:

amazon.com/Step-step-Functional-Verification-SystemVerilog/dp/0981656218

simantis.com

FREMONT, CA - Titan Global Holdings, Inc. has announced that Michael Kadlec has been appointed president and CEO of Titan Electronics, Inc.

Most recently a member of the senior management of Data Circuit Systems, Kadlec has a background in sales, marketing, and communications, and began his career in 1973.

"I am gratified by the support of our board and the opportunity to lead Titan Electronics," said Kadlec. "We have developed a focused and aggressive business plan to build Titan's domestic production at our Fremont plant and our offshore production through strategic partnerships with Asian manufacturers.

Kadlec replaced Curtis Okumura, who resigned from the company.

ROCHESTER, NY – EMA will present a free high-speed PCB design seminar on June 3 in Dallas, Texas. The seminar will discuss the design of system interconnects for complex PCBs, and will use the company's Allegro design platform to manage high-speed constraints, as well as identifying and addressing signal integrity issues in the design process.

The company reports that the seminar will also feature EDA technologies that augment the high-speed PCB design flow, including automating component placement and integrating FPGAs into system level designs. The seminar will conclude with a presentation on verification in the preparation of designs for manufacture.