Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.

These HDI design upgrades are part of the Cadence SPB 16.2 that also addresses chip package design challenges. According to the company, the SPB 16.2 release improves (SiP) miniaturization, design cycle reduction and DFM-driven design. It incorporates a new power integrity modeling solution. These new capabilities can boost productivity of digital, analog, RF and mixed-signal IC package designers involved in single and multi-die packages/SiPs.

Design teams can expect improvements in the reduction in overall package size through the introduction of rules and constraint-driven automation capabilities that address the design methodology of high-density interconnect (HDI) substrate manufacturing that is a key enabler for miniaturization and increased functional density. Overall design time can be reduced through the enablement of team-based design, where multiple designers can work concurrently on the same design in order to reduce design cycle times and speed time to market.