MUNICH, Germany and WESTFORD, MA – Zuken has announced the availability of free footprint data for Altera Corp.’s recently announced low-cost Cyclone III FPGA family. Zuken’s CR-5000 enterprise wide design solution users can download the Cyclone III footprint design templates, eliminating the task of manually entering footprint data into their CR-5000 libraries.

“At Zuken we see it as an important objective to do everything we can to facilitate the adoption of new technology for our customers,” said Werner Rissiek, Zuken general manager of Engineering, Europe. “Through our partnership with Altera, we are continuing to provide the integration needed within the electronics industry for our customers to remain competitive in the marketplace.”

The Cyclone III family is Altera's third-generation of low-cost FPGAs offering lower power with greater logic, memory and multiplier densities than previous generations. The availability of the footprint data as a free download from Zuken is another means to enable the efficient adoption of this new technology.

SYDNEY, Australia – Altium Ltd. announced the addition of new productivity-enhancing features for its Altium Designer unified electronics development system to assist engineers with handling high-speed design issues.
 
Altium Designer 6’s intelligent interactive routing system has been enhanced with the addition of a new interactive length-tuning tool specifically for high-speed designs. This new feature reportedly allows designers to quickly optimize and control net lengths by inserting “accordion” segments into a track. Tuning can be manual or rules-driven, and designers can select from several available amplitude styles. This feature is said to combine seamlessly with impedance-controlled, differential pair and multi-trace routing capabilities to give Altium Designer users a comprehensive interactive solution tuned for high-speed, high-density board design projects.
 
Enhanced control and display over PCB layers will reportedly have more efficient enhanced productivity when moving around large complex designs. The placement and editing of polygons has been streamlined to make the creation of large copper-filled areas fast and intuitive. Improvements have also been made to the way components and libraries are identified and used within the system to deliver greater levels of user control and flexibility. Creating and delivering output for designs that contain embedded board arrays has been improved with added intelligence for identifying layer stackup violations. In addition, enhanced output dialogs for Gerber and ODB++ now reportedly make it even easier for users to make decisions about whether to proceed with output or resolve compatibility violations.