PlanAhead v. 9.2 is an analysis design tool said to promise a full speed grade advantage; features expanded functionality of PinAhead technology, which provides FPGA designers with the ability to assign interface I/O groups to I/O pins by dragging into a graphical representation of the FPGA. Reportedly simplifies the complexities of managing the interface between the designer's target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers. Offers support for the latest Spartan-3A DSP platform FPGA. Supports the entire line of Xilinx Spartan-3 generation FPGAs.
 

 
 
Submit to FacebookSubmit to Google PlusSubmit to TwitterSubmit to LinkedInPrint Article