SM3320S-S single table, SM3350S-D twin table and SM4520L-D twin table floor-mounted printed circuit board depaneling routers feature built-in high-res color CCD cameras with 20x magnification. Program cutting path with controls that are saved, edited and copied. Vision system is included to check fiducials before cutting starts or can be turned off. Precision ball-screw and linear guides maintain repeatability of ±0.03mm. Offer dust collection from the bottom with a built-in ionizer and a safety shield.

Fancort Industries Inc., www.fancort.com

Component Information Portal (CIP) 5.0 is tightly integrated with Cadence OrCAD Capture CIS and EMA EDABuilder for a complete part search and new part introduction flow including automated symbol creation.

Multi-CAD was developed for V5 and V6 users to improve the process of associative design collaboration between CATIA and NX users. Is a V5/V6 plugin that enables CATIA user to work interactively with NX data directly from within a CATIA design environment. Checks geometry for errors; validates integrity of data as it comes into CATIA. Tracks changes and updates master model as each sub-assembly is developed. NX and CATIA files are associative; can output changes back as an NX file or other CAD format.

Theorem Solutions, www.theorem.com

Xpedition Path Finder software suite is for designing printed circuit board assembling and optimizing complex electronics systems, enabling improved design and increased chip performance.  IC layout design data can be represented as a virtual die model, containing IC-level detail specific to co-design and optimization. Board design data can be modeled as individual interfaces or as complete designs. Packages can be built based on pin array and manipulation capabilities, existing devices, and industry-standard formats. Addresses design complexity of system-on-chip and multi-die packaging. Can capture and manage connectivity based on preference. Cross-domain pin mapping and net combining can be managed in all modes of connectivity capture. Can perform rules-based pin/ball-out studies from respective domains, by signal, bus or interface. Automates library development process. Features a correct-by-construction layout environment. Core Xpedition layout tool provides BGA breakout and escape algorithms, coupled with support for microvia structures; shape-based, any-angle routing; plane areas that fill around traces and vias during editing, and RF circuit design and optimization. Rule-based ball-out assignment includes optimization engine/editor for planning by bank, byte, reference voltage, clock domain, etc. Has a single tool for multi-mode physical design (PCB, MCM, SiP, RF, Hybrid and BGA designs). Virtual Die Model captures IC layout design intent and integration with 2D and 3D electro-magnetic and computational fluid dynamics thermal analysis engines.

Mentor Graphics, http://www.mentor.com/