The coronavirus has spread to over 200 countries and claimed more than 30,000 lives.
The virus emerged in China in December and spread around the world. European countries and the US report a significant amount of cases over the last two weeks. The total number of the cases is more than 600,000.
I traveled to our home office in Japan last week. The number of the cases in Japan jumped up significantly in the Tokyo area last week. I have no symptoms of coronavirus infection, but remain in self-isolation for at least two weeks. I will refrain from public transportations including taxicabs.
Market analysts predict a slowdown in the global electronics industry due to the pandemic. Stock markets throughout the world are experiencing extreme volatility with every news report. The Dow Jones fell almost 25% YTD. It’s at its lowest level since December 2016, and is on pace for its worst month since the Great Depression.
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A look at how array technology influences processes from board routing to drill to test.
“Miniaturization has made it possible for electronics to penetrate society more widely and deeply than ever before.”1 That sentence is as relevant today as when it was written in 1984. It embodies the core tenets of Moore’s law, and the associated manufacturing technologies that have enabled performance improvements in electronics at a predictable cadence for 55 years: 1) decreasing feature sizes, 2) increasing functionality, 3) decreasing cost. One of the most important innovations to accommodate increasing densification of chip technology has been the ball grid array, introduced in the early 1990s, which permits high pin counts per area relative to peripheral lead and no-lead packages such as QFNs and DFNs. The evolution of array packaging has moved from BGA to chip-scale package, to wafer-level CSP to flip-chips, defined by a steady march toward smaller balls and finer-pitch arrays (FIGURE 1).
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The year is flying by. The first quarter is close to completion, and 2019 is a distant memory.
Analyzing business trends and forecasting is difficult enough without adding a wild card into the equation, specifically the coronavirus. For this reason, I decided to provide a snapshot for the industry prior to coronavirus, and look at trends moving forward.
A slowdown for consumer electronics began during December 2018. Global shipments for semiconductors and printed circuit production in Taiwan declined sharply and continued over the next few months. The industry noticed a rebound during the second quarter of 2019, but declined again during the last quarter of the year.
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New 3-D technologies with robust interconnects and thermal solutions are on the way.
Ed.: This is the fifth of an occasional series by the authors of the 2019 iNEMI Roadmap. This information is excerpted from the roadmap, available from iNEMI (inemi.org/2019-roadmap-overview).
Aerospace and defense (A&D) products face several challenges unique to this particular market segment, including the extreme environments in which they operate, need for security, desire for reworkability, long duration storage requirements and the functional lifetime over which the products are expected to perform and be supported.
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Written by Binghamton University and Integrated Electronics Engineering Center (IEEC)
Category: Features
Updates in silicon and electronics technology.
Ed.: This is a special feature courtesy of Binghamton University.
Transistors can process and store information. Purdue University researchers have created a feasible way to combine transistors and memory on a chip, potentially bringing faster computing. They used a semiconductor that has ferroelectric properties. This way two materials become one material, and without worry about the interface issues. The result is a so-called ferroelectric semiconductor field-effect transistor, built in the same way as transistors currently used on computer chips. The material, alpha indium selenide, not only has ferroelectric properties, but also addresses the issue of a conventional ferroelectric material usually acting as an insulator rather than a semiconductor due to a so-called wide “band gap,” which means that electricity cannot pass through and no computing happens. (IEEC file #11468, Science Daily, 12/9/19)
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There are several theories about whether a differential pair should be routed with tight coupling or loose coupling. There must be some science that can be drawn on to arrive at a rule set that makes best use of layout time, while optimizing the signal integrity of a differential pair. This article explores the advantages of tight and loose coupling.
A known industry speaker says, “Everybody knows tight coupling is best for differential signaling.” This is stated in a tone of voice that implies those who don’t know this might be lacking. I sometimes say I am from Missouri, which is the “Show-Me State.” If the need for tight coupling is true, perhaps there is some proof. I am still waiting to see it. The following discussion will look at a tightly coupled differential pair and the same pair loosely coupled.
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