ENDICOTT, NY – Endicott Interconnect Technologies has released HPC-Z interconnections that provide signal connections only where desired, with functional isolation for single or double side surface mount partitions.
 
The HPC-Z interconnect reportedly solves thick board drilling and wire density problems with the capability of isolating high-speed channels on one sub-assembly and low-speed channels on another. It provides interconnections within the board, and eliminates unnecessary plated-through-hole (PTH) drilling.
 
“Now, you only laser drill the length of the sub-composite,” said Voya Markovich, CTO and senior vice president of R&D. “You can eliminate PTHs that are blocking other wiring channels, which increases wireability, eliminates PTH stubs and results in a thinner and faster board. We’re working to develop full HPC–Z products that will completely eliminate the need for mechanical drilling and result in the introduction of higher density and higher speed integrated electronic packaging products.”
 
HPC-Z provides a “PTH-like” connection at lamination with a pad-to-pad connection made with conductive epoxy. Since there is vertical connection with a lamination in place of a PTH, aspect ratios for drill and plate are limited to sub-assembly dimensions. Drilling is reduced; instead of having to drill a 300-mil-thick board through the entire structure to go from signal plane to signal plane, you can drill only where necessary. This minimizing of the PTH effect results in increased wiring density due to smaller vias and lands. With HPC-Z, there are more wiring lines available that would have been closed off by PTH drilling.
 

SANTA CLARA, CA – Sigrity Inc. has introduced OrbitIO Planner, a solution that is said to enable dynamic IO planning across the multiple domains of IC, package and printed circuit board. According to the company, this is the first single tool to provide both a full physical view of all the interconnect domains that comprise a system, and offer the ability to explore and optimize the IO interfaces across these domains.
 
OrbitIO Planner reportedly addresses the discontinuities that exist in today's design flows by providing a 'big-picture' system view early enough in the design cycle that meaningful changes can be evaluated easily and propagated among domains. The foundation for this capability is a unified data model that merges all of the IC, package and PCB data into a single data representation, using their native formats. This single data model facilitates real-time evaluation and what-if exploration of IO assignment and connectivity options.  Once the optimized IO plan has been established, the data is pushed back to the originating sources in their native formats.
 
"The traditional approach to IO planning using spreadsheets and snapshots of static data no longer is viable, as more and more companies face product delays, cost issues and overly complex designs as a result of poor planning,” said Dr. Jiayuan Fang, president of Sigrity. “Package awareness in IC tools is a step in the right direction, but it's limited by the tools' single-die orientation and an inability to plan for multi-die applications such as system-in-package (SiP) or package-on-package (POP). We're pleased that early customers are taking an IO-centric approach to design planning by implementing OrbitIO Planner as the first step in their physical design planning process."
 
OrbitIO Planner can be applied to a wide variety of package configurations, including stacked applications for SiP and POP. It also supports wire bond, flip-chip, surface mount and mixed-die-attachment methods. OrbitIO Planner is compatible with IC design flows from Cadence, Magma and Synopsys, using standard formats such as LEF/DEF and Open Access, and it supports package and PCB data for most popular systems.