SANTA CLARA, CA -- Sigrity, Inc. announces the release of Channel Designer, an analysis solution that offers the flexibility and accuracy required for high-speed serial links.

"Our customers have found that designs with high-speed serial links operating at multi-gigabit speeds require more than traditional analysis," said Dr. Jiayuan Fang, president of Sigrity. "It is essential to accurately predict bit error rate to ensure a robust implementation that can handle anticipated jitter and noise levels. With millions of bits of data to be considered over a wide frequency spectrum from DC to tens of gigahertz, it can be extremely challenging to obtain reliable time-domain simulation results from band-limited channel models. Channel Designer provides unparalleled precision, and builds on Sigrity's long-standing strength in S-parameter handling for accurate system-level transient simulation."

According to Sigrity, the analysis solution provides support throughout the process, from feasibility studies through design verification. The channel analysis output includes 2D and 3D eye diagrams, along with bathtub curves, for accurate bit error rate prediction.

The channel design capture environment includes a net-based, block-wise schematic editor for designs ranging from a single net interconnect to an entire bus traversing multiple boards. The analysis solution provides high simulation accuracy for accurate transient simulation for designs from DC to 10 gigahertz and more.

The analysis solution uses an industry standard IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver model plus unique capabilities such as cascaded model support to simplify the flow.

SAN JOSE, CA -- Force10 Networks announced it has been awarded a patent (US Patent 7,448,132 - "Method of Manufacturing a High-Layer-Count Backplane") for its backplane circuit board design and manufacturing method for high performance switch/routers that uses a three ounce or more copper weight in a high-speed, high layer count design.

“These backplane fabrication innovations are critical to advancing our technology to ensure we’re supporting the increased traffic throughput needs of our customers at the lowest total cost of ownership,” said Joel Goergen, Force10 Networks Chief Scientist. “New and emerging applications are placing unprecedented demands on networks, while managers, more than ever, are tasked with building a cost-effective, resilient, and reliable infrastructure -- and this patent is an additional step in meeting both goals.”

The fully passive copper backplane reliability delivers a throughput of five Terabits per second. The patented fabrication method uses three ounces or heavier copper weight in a high-speed, high layer count design where there is both primary and secondary power, eliminating the need to utilize busbar technology or separate power boards to route the power. This patented capability facilitates the ability to build a single, lower-cost backplane solution for signals and power.