DDR Debug Toolkit, for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals, provides test, debug and analysis tools for the entire DDR design cycle. Read and Write bursts can be separated and eye diagrams for each can be displayed in real time, providing unique insight to system performance with a single push-button. Identifies root causes of problems with jitter analysis specifically designed for bursted DDR signals that conventional serial data tools cannot analyze. Includes a variety of built-in DDR-specific measurement parameters, enabling easy quantitative analysis of system performance. Performs DDR analysis simultaneously over four different measurement scenarios, improving DDR testing efficiency and providing faster results. Displays up to 10 eye diagrams simultaneously. Multi-measurement scenario analysis capability lends itself to optimization and tuning of system and device performance, while the built-in measurements provide characterization benchmarks for precompliance testing. For testing to JEDEC standards, analysis tools can be leveraged to perform margin testing and to troubleshoot failures which arise during compliance testing. Provides alternative to automated DDR compliance test packages for times when full compliance testing is not required.

Teledyne LeCroy, teledynelecroy.com

Pulsonix 8.5 schematic capture and PCB layout tool features new  Panel Editor enabling multi-board designs to be panelized for plotting, plus the addition of test coupons, fiducial markers, documentation and fabrication details. Offers IPC-2581 netlist export and Gerber X2 manufacturing outputs. Imports library formats from PCB Libraries, Accelerated Designs and SnapEDA.  Library manager enhanced to allow drag-and-drop methodology from native ASCII files directly into the library. Adds cyclic design backups and security saves, cross probing of Star (Delta) Points, individual width and offsetting of cross hatching, additional DRC checks, import PCB component placement CSV format and multiple group selection for design reuse in Apply Layout pattern as well as multiple positional rearrangement optio

Westdev Ltd., www.pulsonix.com

DF65 Series connector is a vertical-mating wire-to-board connector that provides high-current capacity and high reliability for power supplies, up to 4A (with 24 AWG wire) and 50V AC/DC. Features a 1.7mm pitch and 1.8mm mated height. Vertical mating maximizes board space and reportedly reduces assembly time. Has locking system for high-vibration; is suited for use with a DC jack or battery pack. Double-locking structure reinforces engagement between socket and header. Positive lock secures socket into header; produces over 5N cable pull strength in the upper direction. Friction lock system produces final click; prevents socket from floating after mating. Has operating temp. range of -35° to +105°C; limits contact resistance to 10M ohms max. with an insulation resistance of at least 100M ohms min. at 100V DC. RoHS compliant.

Hirose, www.hirose.com/us

PE510 copper conductive ink is for antenna, membrane touch switch (MTS), radio-frequency identification (RFID), and consumer electronic applications. For processing low-lamp-voltage copper metallization circuit designs on a range of substrates including FR-4, PVC, polyimide film and PET.  Can be processed using high-speed photonic curing equipment and provides a long lamp life as well as superior adhesion and processing. Achieves high printed line and space resolution. 

DuPont Microcircuit Materials, mcm.dupont.com