Chip caps help only if the conduction in the path is sufficient to deliver the right charge.
Much of the talk in the simulation world lately is focused on power. Even SI experts are starting to see how power has a material impact on their high-speed data transfer success. With power on the forefront, what effect will that have on the additional design demands of low-frequency supplies? Why should you consider power throughout your design process?
Signal integrity, at its basic core, studies and describes the effects physical structures have on a signal, as it is transmitted from a source (transmitter) to a destination (receiver), but makes no mention of where the energy for the signal originates, or where it goes once received. Although a bit of oversimplification, the transmitting IC pulls energy from its power supply, bundles it as a bitstream and transmits data to a receiving IC, where the energy is dumped onto the ground and eventually returns to the power supply, ready to repeat. Admittedly, today’s high-speed signals are largely differential and draw from multiple power rails, so we aren’t describing the exact current flow. What we are describing is the notion that reliable data transmission involves both a clean path from driver to receiver in addition to a well-designed plan to deliver and return needed power.
In our previous column related to power distribution (PCD&F, April 2021), we discussed capacity. Specifically, we focused on the increasing current demands associated with most new designs and showed the need to ensure our conductors (pins, planes, vias, and etch) were up to the challenge. Today we add another requirement: responsiveness. Even an IC with ample current supply could experience “power shortage” if the energy needed to transmit the data bitstream isn’t available in time.
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