Many new products need tighter hardware.
Two compelling forces driving much of our technology – miniaturization and performance – are not new. In fact, one could say they have appeared within every product spec and design document in some form or another since the terms were coined. Fundamentally, this has enabled capability and portability with products in virtually every hardware sector. This will (and should) continue. In the area of miniaturization, both board and package are transforming as technologies such as rigid-flex, blind/buried vias, and multi-die packages move from fringe to mainstream. Further, performance improvements maintain the well-known doubling trajectory and are propelled forward by orders of magnitude in speed, while increasing efficiency and extending battery life. Often these gains are continually achievable only by reducing the voltage swing to under a volt. As miniaturization and performance drive devices to new functionalities and applications, the effects of these requirements are visible throughout the design process. Nowhere is this drive for smaller, faster, cheaper more noticeable than in power.
Power demands outpacing supply. To comprehend the extent of the power delivery network (PDN) transformation, consider the following. Design requirements associated with power delivery have become substantially more complex, with many ICs requiring power to be supplied at multiple voltage levels. Frequently those levels are near or below a single volt, contracting virtually every threshold and reducing margins to mere millivolts. Simultaneously, demand for current has skyrocketed in some product areas, made obvious by the extent to which we now account for adequate cooling. In addition to these increased electrical demands, the PDN must also be more responsive, capable of supplying the instantaneous current demands of high-speed signaling. While all this may suggest a more robust PDN is needed, as many new products reach manufacturing, often the opposite is true. Not surprisingly, the miniaturization effort has had a consolidating effect on the physical hardware, frequently bringing high-current ICs closer together (FIGURE 1). Advances in device packaging have contributed as well. Pin counts can easily exceed a thousand on a single package, and mainstream spacing under a millimeter contributes to the same reality: The PDN is comprised of less copper in today’s PCB than it was just a few years ago.
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