UCIe 3.0 is where bandwidth meets bravado.
In August, the Universal Chiplet Interconnect Express standard revision 3 was issued. This follows revision 2 by exactly a year. The first selling point of revision 3 is higher data rates, double that of the previous version. If that sounds like another standard, PCIe, then chalk it up to UCIe using PCIe as a template, along with the Compute Express Link (CXL), to build the UCIe ecosystem. It remains adaptable and scalable according to needs.
The founding members make up some of the titans of their respective industries. You’ve heard of them and likely others who have signed up to support version 3. It’s more than the bandwidth. The sideband channel is upgraded so that:
- “Priority sideband packets permit deterministic, low-latency signaling for time-sensitive system events.” An important background command can be expedited to keep things running efficiently.
- “Fast throttle and emergency shutdown mechanisms provide immediate system-wide notifications via open-drain I/O.” Dovetails with the bullet above, where the system can manage thermal shutdown issues.
- “Support for continuous transmission protocols through mappings, enabling uninterrupted data flow in Raw Mode.” This feature enables ADCs to get the uninterrupted feed rate required for seamless operation.
- Backwards compatible with existing UCIe protocols.
These are among several other changes that separate version 2 from version 3. The spec is broken down into two general connectivity schemes: UCIe-S (Standard Package, 2D) and UCIe-A (Advanced Package, 2.5D).
Figure 1. The bump pitch for either technology seems ridiculous for a PCB designer. Additive technology can do some fascinating stuff. (Source: Dr. Debendra Das Sharma; V3 press release, snipped from a larger table.)
The concept of heterogeneous integration is not so new. My jumping-in point was around the turn of the century. Big Bear Networks was a startup doing all sorts of innovative things in the optical space around OC192 and OC768 specifications. This is where 10Gb/s and 40Gb/s come into play. We had a multichip module (MCM) with two chips and a row of tiny passive components. The first chip consumed a single pair of 40G transmission lines and would output four lanes of 10G. It had the usual complement of control lines and a PLL (phase locked loop) circuit. The other chip drew directly from the four 10G feeds and provided four lanes at 2.5Gb/s, each for a total of 16 differential pairs over copper from a single fiber. Around the data center, things will be an order of magnitude more intense. The distinction between board and substrate materials (and processes) is starting to blur. This MCM used LTCC (low-temperature co-fired ceramic) material for the dielectric.
Another project used thin film. It was kind of like building a jigsaw puzzle one tiny circuit at a time. I was creating these little squares, each with a primitive circuit that fanned out to wirebond pads. The small pieces were attached individually to a substrate, then components and wirebonds were added to complete the circuit assembly (Figure 2).
Figure 2. An assortment of primitive circuits was cobbled together and connected with wirebonding. Size limits for thin-film technology meant only the smallest packages were supported. Chiplets use flip-chip technology, whereas this experiment is set up for wirebond connections using packaged electronics. (Source: Author)
I had no idea what we were doing until I saw the mosaic of little circuits where my job was to create a wirebond diagram. After spending a summer as a tile setter’s helper, I looked at the different circuit patterns as tiles. The most popular tile had a resistor footprint, a test point and two wirebond pads. Anyway, the EE did the “tile setting” with the schematic in his head at that point.
Looking at many different chiplet configurations online, the substrate layout mirrors what we do on a PCB, except with each chiplet in its own package. To that end, routing priority goes to the memory cache while the quiet zone is occupied by wireless technology. It comes down to small-scale board design.
Chiplet edges are called the beachfront. It’s where the spec defines the interaction. Standard density yields 16 I/O pins, while the advanced density uses 64 I/O pins with the same length of beachfront. The miracle is in the interposers (Figure 3).
Figure 3. The UCIe interconnect diagram showing the main band and side band connections between two chiplets with “standard” organic substrate material. Using “advanced” material enables 64 data I/O lines rather than the 16 for organic. (Source: Cadence)
The interposer game has a few main players. TSMC with its “CoWoS” (chip on wafer on substrate) family and Samsung with the “Cube” series seem to have the lion’s share of the pie. Intel also created a standard that it shares. There are a couple of standards for optical gear as well. They all operate in their specific ways while underpinned by the UCIe standard.
Another standard is called Bunch of Wires. I like the transparency. It is strictly a PHY specification that could lean into the UCIe standard for the die-to-die adapter and protocol layers (Figure 4).
Figure 4. The minimalist version of Bunch of Wires implementation using a “full slice.” The term “wires” refers to traces on the interposer. This could also be cut to eight lanes on each bunch for a half slice. Of course, it can be scaled up as well. We currently have BoW-32, -64, -128, -256, -384 or BoW-512 for increased throughput. (Source: OpenCompute.org)
Chiplets are pushing substrate design to a whole different level beyond the SoC (system-on-chip). So many more options exist beyond the monolithic silicon die. Challenges remain for qualifying a mix of various chiplets. The SiP (system-in-package) designer must address thermal and signal-integrity concerns when integrating a diverse chipset into a single package. The extra freedom can be a blessing or a curse.
Whether the device will use organic material or a silicon interposer is the dividing line between standard and advanced package solutions. Just as in PCB design, each circuit block location has an oversized impact on the overall SiP design outcome.
I’ll leave this conclusion from the standards committee: “UCIe 3.0 represents a transformative advancement in chiplet interconnect technology, addressing the critical needs of modern computing applications. By doubling data rates, supporting continuous transmission protocols, optimizing power savings, and enhancing manageability, UCIe 3.0 sets a new standard for efficient, scalable and reliable chiplet integration.”
John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. His well-earned free time is spent on a bike, or with a mic doing a karaoke jam.
