2012 Articles

Most product cost is determined in design, before it ever reaches production.

OEMs constantly seek ways to cut product cost and time-to-market. The advantages of a shorter time-to-market and lower costs of an end-product are evident: market attraction improves, lifecycle extends, development cost reduces, etc. This is far from a trivial mission, and different managers look for different ways to achieve these objectives. One strategic path leading to attaining these objectives is DfX methodology. DfX (Design for Excellence) is an efficient tool with a proven record of accomplishment with which we can ensure proper execution of electronics products the first time.

Research indicates that OEMs that develop electronics products and have implemented DfX methods stayed within 82% of their development budget, performed 66% less repair rounds and saved $26,000 in those rounds they did perform.1 Other scientific work2 indicates that approximately 75% to 85% of the cost of an electronic product is determined in the design phase, while the actual product costs increase significantly, of all places, during production (Figure 1).



As the design process advances, the window of opportunity to introduce changes becomes smaller, and the cost of introducing change grows, in some cases exponentially. For example, introducing a change after putting together a prototype will entail a new PCB layout round, execution of an engineering change order (ECO), ordering a replacement version, reproduction, inspection of quality and reliability, renewed meeting of standards, delay in supply to customers, etc. In other words, taking into consideration problems that may arise during production and assembly during the design phase proves to be an efficacious method for reducing costs and increasing yield.

It is true that implemention of DfX requires further investment of time by the organization during design, yet research indicates that as a result of this extension of time, the product’s overall time-to-market drops by approximately 40%.3

This requires an understanding that quality control, by itself, does not suffice for the task of prevention of problems. The fundamental of success of an electronics product is a sound design, maintaining an open and productive channel of communication between the designers and production, based on accumulated knowledge and experience. As part of DfX, we remain aware that failure may occur in the future, and implement working methods to prevent it from happening.

Failures in design of the electronics product can take place due to incomplete exchange of information between the electrical, mechanical and PCB layout design; failure to understand the shortcomings and capabilities of production; and unrealistic customer expectations regarding the process of development of a new product in matters of reliability and time-to-market. DfX’s purpose is to ensure consistent and continuous production throughout the supply chain, with a minimal number of failures.

The DfX methodology consists of several sub-topics, according to the various stages in the product lifecycle. Every topic relates to a different stage in the production cycle and is accompanied by instructions pertaining to the actions to be taken in the design stage to prevent failures. These topics include DfM (design for manufacturing), DfT (design for testability), DfR (design for reliability) and DfE (design for environment).

To demonstrate this, following are several key rules how to properly implement DfX.

Learn from the past. Albert Einstein said, “The only source of knowledge is experience.” When developing new products, consult the past. Failure to meet quality, customer complaints, reasons for product recall, and so on are all sources of information to draw from. To this end, we are required to document such incidents in an orderly way, analyze them and implement procedures that will prevent their recurrence. A cross-organizational brainstorming of every element taking part in the project may well be a way to achieve this.

Stick to norms as much as possible. Adhere to standards as much as possible at all stages of product development. This is true when engaged in design, layout, choice of components, procurement, production processes, etc. Developing product using existing standards helps cut time-to-market, simplifies processes and minimizes risk of errors. Take, for example, a non-standard component. If we choose a component failing to meet the norm, we expose ourselves to a higher price tag, because the part is less common among all the suppliers, thus less governed by laws of competition and (likely) produced in smaller batches. Second, as a result of the need to replace the item, the time to deliver may stretch, and consequently, we may presume that the supply chain will be disrupted. It may be difficult to find a substitute component. Avoid reinventing the wheel; stick to norms as much as possible.

Reduce the number of components in a product. One of the best ways to reduce production costs and enhance product quality and reliability is to reduce the number of components. When using fewer components, the cost of acquisition may be reduced by placing a large order of one item, rather than a small order of several items. In addition, as the number of components in an electronic circuit determines the assembly cost, reducing the number used will lower that cost, respectively. Further, reducing the number of components will result with less risk of faulty items and quality issues during assembly. Consider these examples: First, designated component library, including an AVL (approved vendor list), ensures that a new product would use known components. Second, components that can be used in several applications may cause an increase in direct costs, but in general, the overall cost of all the components will decrease. Third, ordering whole assemblies from a subcontractor avoids dealing with putting together these subassemblies.

Design for Lean production. The main principle of designing for Lean production is that whatever does not add to the product’s value is garbage to be discarded.
As part of this design, cut down on production processes as much as possible through use of automatic assembly over manual (e.g., SMT components instead of manual insertion through-hole parts). The manual assembly to be performed should be simplified to such degree as to avoid questions and errors, as well as to help turn assembly automatic at a later stage. Refrain from additional production processes, where possible; e.g., design boards with components on one side instead of both sides by reducing the area of components or increasing the area of the printed circuit board. Design for Lean can help save a great deal of time in production and improve product quality.

When it comes to production, stay away from technological extremes. Make a distinction between the product’s development and its production. When we develop the product, we may be interested in taking the technology to an extreme to differentiate our product from competing products in the marketplace, as well as to offer our customer added value. In its production, we should take the opposite approach. Since production is not added value for us, we should simplify it and base it on existing technologies, ensuring higher quality and reliability. So, for example, choosing a component with a 0.4mm pitch would be preferred over a 0.3mm pitch component; a 0402 package would be a better choice than a 0201 package, and choosing a 10 mil trace width would be better than choosing an 8 mil.

Develop work methods to nullify failure. As we know, Murphy’s Law never rests. If anything can go wrong, it will. Anticipate failures and work to prevent them from happening in the first place. For instance, a clear and comprehensible product assemble file should be prepared for every worker of the production line. To avoid confusion and interference, the instructions should be specified in a methodic and unequivocal way. To prevent duplication, instructions should be listed only in one place in the file. Reduce text use as much as possible; use images and visualization in its place. In this context, it would be advisable to plan the product’s assembly process so it will be assembled in no way but the proper one. Improper assembly should be prevented by employment of asymmetric holes, stops, etc.

Integrate and coordinate design and layout elements and production and assembly elements. Whenever a PCB is designed, its production should be taken into account from the start. The planning and layout teams should be synchronized at the best possible level with the production and assembly teams. To reach a complete optimization of the circuit and electronics product throughout production, initiate thinking processes, combining the planning and PCB layout with production and assembly elements. Ensure that every critical objective of the process is known, considered, controlled and eventually, achieved. These objectives include product cost, desired level of quality, reliability, regulation, time-to-market and customer satisfaction.

The great victors of today’s competitive technological world are those companies that can deliver to their customer an innovative product that holds an added value over their competitors. Development of an innovative product is an imperative but insufficient condition to attain these objectives. Organizations wishing to achieve these goals should reduce their production costs and shorten the product’s time-to-market. Implementation of DfX will improve company performance by ensuring the right job is performed correctly from the beginning.

References

1. Aberdeen Group, “Printed Circuit Board Design Integrity, The Key to Successful PCB Development,” 2007.
2. Martin Tarr, “The DfX Concept,” University of Bolton, 2007.
3. D. E. Carter, and B. S. Baker, Concurrent Engineering: The Product Development Environment for the 1990s, Addison-Wesley Publishing, 1992.

Arbel Nissan is COO at Nistec (nistec.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

In 2012, PCB designers say their salaries are rising and their challenges are staying the same.

If PCD&F learned anything from this year’s designers’ salary survey, it’s that the overall picture looks remarkably similar to that of 2011.

In late February through March, PCD&F compiled data from 467 bare board designers. The survey, which was conducted online, covered salaries, job functions, titles, types of projects, benefits, education, experience, career concerns, and location, to name some. Results are intended to paint a portrait of the status of design industry jobs, as opposed to a thorough scientific account.

Sixty-eight percent of the 467 respondents listed their principal job function as PCB design and layout – the most common response by far (Table 1). Next was “PCB layout only,” which garnered 9% of responses, flat with 2011, followed by design/layout management (8%, up two points from 2011), and PCB engineering (5%, down from 8% last year).



Of those surveyed, 56% are senior PCB designers, down just one percentage point since the 2011 survey (Table 2). The second most selected job title was PCB designer, with 15% of responses, compared to 12% in 2011. Design engineers make up 7% of this year’s respondents, down from 9% in the last survey. Other job titles in 2012 include PCB design manager (6%), senior engineer (4%), hardware engineer (4%), CAD librarian (3%), electronics technician (2%), principal engineer (1%), and “other” (1%).



Designers are still predominantly a veteran crowd, with 53% (compared to 54% in 2011) indicating more than 20 years’ experience in the industry. Twenty-one percent of respondents say they have more than 30 years under their belts, up from 18% in 2011. Sixteen percent indicate 11 to 15 years, 21 to 25 years, and 26 to 30 years, respectively, while 13% say they’ve been in the business for 16 to 20 years. Seventeen percent surveyed are relative newcomers, with 10 years or fewer of experience (3% more than in 2011); only 7% of those respondents indicate five or fewer years.

In response to reader requests, PCD&F sought more detail on where respondents are located with this year’s survey. As with last year, most who took the survey are located in the US (73%); this figure is down three percentage points from 2011 (Figure 1). This year, PCD&F also broke the US into regions. Twenty-three percent of respondents are located on the West Coast (including Arizona). Eighteen percent are in the Northeast/New England/Mid Atlantic section of the US, while 15% live in the Midwest. Eight percent are in the Southeast part of the US; 5% are in the Rockies region, and 4% live in the plains states. 



Nine percent of respondents live in Central/Western Europe; 6% are in Canada; 3% are in Southeast Asia (not China), and 3% checked “other.” Only 2% of respondents reside in Mexico and Africa/Middle East, respectively. One percent live in Eastern Europe. Other areas of the globe are not statistically represented in the responses.

The bare board design field continues to be dominated by men; 86% of respondents are male, compared to 88% last year. And the industry is still aging. Fifty-five percent of respondents fall between ages 46 and 60, and another 10% are between 60 and 70-years-old. Ten percent are 41 to 45; 9% are 36 to 40; 7% are 31 to 35, and another 7% are 26 to 30. Only 1% of respondents are under 25. The same question continues to loom: With more designers reaching retirement age than those who are poised to replace them, what will the implications be in the next decade or so in terms of qualified workers? Educators, take note.

Designers still mostly work for OEMs (66% this year compared to 67% last year). Ten percent say they work for design service bureaus, flat with 2011 (Table 3). Six percent work for both, also the same as last year. Two percent work for EMS firms, compared to only 1% last year. Another 2% work for PCB fabricators, and 2% more work as consultants.



All end-markets are represented by the respondents, and the population by sector generally reflects the overall electronics end-market breakdown by revenue. The largest percentage of respondents, 23%, design high-reliability products (Table 4). Meanwhile, consumer electronics (including white goods) makes up 11%.
Large companies continue to dominate. As in 2011, 40% of survey respondents work for companies that have more than 1,000 employees. Eighteen percent work at firms with 251 to 1,000 staff members, compared to 19% last year. Merely 14% work for companies with 25 or fewer employees, down two percentage points from 2011. Thirteen percent are among a staff of 101 to 250.



Surprisingly, a full quarter of respondents are unsure of their company’s approximate annual sales. Eighteen percent say they work for a firm with $5 billion or more in sales, up three percentage points from last year. The third highest response was $5 million to $49 million, with 15%. Nine percent work for a firm with $1 billion to $4.9 billion in sales; another 9% work for a firm with $100 million to $499 million in sales; 8% said $50 million to $99.9 million, and 7% indicated $500 million to $999 million. Only 9% work for a firm with sales less than $5 million, down from 13% in 2011.

Pay Hikes

The survey asked respondents to characterize current annual salaries in US dollars in five- to ten-thousand-dollar increments. Seventy-three percent say their salary exceeds $60,000, the same percentage as in 2011. Some 28% say their salary tops $90,000, down two percentage points from last year, with 17% of those respondents making six figures – up from 12% last year. Twelve percent make $30,000 or less, with 8% in the $20,000 or below range.

In the past 12 months, 69% of respondents saw their pay increase, compared to 70% at this time in 2011. Of that 69%, the bulk received raises of 1 to 6% (Figure 1). Five percent say their salary increased 7 to 10%, and some 6% saw pay raises of more than 10%. Seven percent indicated a salary drop in the past 12 months, up from 4% last year. The remainder say their salary hasn’t changed.

More than half (56%) of respondents didn’t see a bonus in the last 12 months, compared to 53% last year. Of those who did receive a bonus in the past year, 43% say it was 1 to 3% of their salary, up one percentage point from 2011; 29% say it was 4 to 6% of their salary (same as last year), and 28% received a bonus of more than 7% of their salary, down two points from the 2011 survey.

Health insurance topped the company benefits once again with 87%, up two percentage points from last year’s survey. Dental insurance coverage is provided to 75% of respondents, compared to 73% last year. Life insurance received 73% of responses, compared to 70% in 2011. Sixty-six percent say they have the option of a 401(k) or other savings plan, down two percentage points from the previous survey. Other benefits include an onsite cafeteria (50%); a stock purchasing plan (36%); an exercise facility (33%); a company pension or retirement plan (28%); telecommuting (24%); profit sharing (23%); relocation expenses (16%); sabbatical (6%); daycare (4%), and 7% of respondents say they do not receive any of these benefits with their firm, compared to 9% last year.

When asked about the biggest challenges designers expect to face in 2012, “workload” is still the top response with 49% of responses (Table 5). Technology is second, at 36%. A close third is keeping one’s job, with 34% of respondents concerned about their job security. Twenty-five percent say outsourcing is their biggest concern, and 7% say “other.”



The survey again asked designers what types of technologies they directly engineer, design or layout. As in 2011, the most responses went to 4 to 6 layer PCBs (84%) and double-sided PCBs (81%). Seven to 10 layer boards garnered 61% of responses; 58% say BGAs; more than half also work with 12 plus layer PCBs (53%); 47% of people say single-sided PCBs, compared to 51% last year. Other responses:

Flex/rigid PCBs: 44%
Microvias/HDI: 38%
FPGAs/PLDs: 36%
RF/microwave circuitry: 36%
ASICs/ICs: 28%
Embedded systems: 15%
Chip-scale packages: 11%
SiPs: 10%
Hybrids: 9%
MCMs: 9%
SoCs: 9%
None of the above: 1%

The number of new designs produced each year could be increasing based on the numbers. Six to 10 designs is still the highest response, with 29%, up from 27% in 2011. Eleven to 15 came in second with 18%; 14% say 16 to 20; 8% say 21 to 30, and 16% produce more than 30 designs each year. This figure is 5% higher than last year. Only 15% say 1 to 5 designs, which is 3% fewer than 2011.

The picture of education looks very similar to the responses in 2011. Again, only 5% say their highest level of education is a high school diploma. Sixty percent have “some college” or an associate’s degree, down from 62% last year. Twenty-one percent have a bachelor’s degree in engineering, flat with 2011. Only 5% have a bachelor’s degree in a non-engineering field, down one percentage point from the previous survey. This year, 9% say they have a master’s degree, which is 3% more than last year. Two respondents say they have a Ph.D.

The majority of companies encourage continuing education, with 55% of respondents saying their firm provides tuition reimbursement, down two points from last year. Fifty-three percent receive on-the-job training, and 45% indicate they have the option of attending classes at conferences, both flat with last year’s survey. Forty-one percent have company-sponsored classes; 28% have mentoring; college classes are supported by 21% of companies, while 20% of them do not provide any of these educational opportunities.

Slightly more respondents in this year’s survey have management responsibilities, but the majority are still not responsible for managing others. Seventy-six percent do not have other staff members reporting to them, compared to 79% last year. Nineteen percent say 1 to 5 people report to them, up 3% over 2011. Four percent say 6 to 10 people report to them, and only 1% are responsible for 11 to 20 other employees. One person who responded to the survey manages more than 20 people.

Thirty-three percent of respondents are IPC certified designers, compared to 36% on the last survey. Seven percent say they were laid off in the past 12 months, compared to 6% in 2011. A whopping 91% say they have the same job as they did at this time in 2011.

Of those who can recommend or approve product purchases, most get to weigh in on software tools. (Table 6). Twenty percent evaluate products, and 17% specify products. Eight percent can approve product purchases, and 19% lack authority to perform any of these functions, compared to 16% in 2011.
Designers’ jobs and salaries look stable for 2012; the positive improvements that began in 2011 have maintained steadiness.



To view results for the 2011 survey, visit http://pcdandf.com/cms/component/content/article/237-2011-issues/7995-cover-story.

Chelsey Drysdale is senior editor for PCD&F; This email address is being protected from spambots. You need JavaScript enabled to view it..

3D structures on high-speed signal paths can significantly influence transmitted signals.

Those involved in board analysis during the past 10 years will have noticed changes in signal speed and design applications. The dominant high-speed applications are high-speed memory designs and gigabit-per-second channel designs. At the end of the last century, engineers started routing differential signal nets on PCBs that could transfer data at rates exceeding 1 Gbps. The signals at such speed were initially used to build boards and backplanes in large communication systems. Demand for increasingly fast computation and information transmission continues to increase, with a substantial number of designs operating at multiple Gbps range. Advanced memory designs are moving data at 10 Gbps, and the latest SerDes communication standard is reaching toward 30 Gbps.

With signal speed changes come new challenges of solving design issues never seen before. The components of signal paths on boards and interconnects present problems, such as significant dielectric loss or impedance discontinuity from non-trace portion, which used to be ignored at lower signal speed.

Figure 1a illustrates the three-dimensional cross-section of an IC with a SerDes channel, showing the die, its associated package and pins (or balls), the PCB, and the mechanical mounting of the package on the PCB; Figure 1b shows the electrical equivalent circuit. In this example, the impedance discontinuity contribution comes from the vias for signal switching layers, connectors enabling multi-board connections, and packages. To PCB designers, only via configurations are under their control in these discontinuity contributors.



Via modeling. To understand modeling of the vias used in simulation, we’ll begin with a single via in a PCB stackup. Figure 2 is a schematic representation of the equivalent circuit. With slower speeds (that is, slower rise and fall times) common up to a few years ago, via effects were not significant enough to be concerned. Now, with signals having rise/fall times around 100 ps, via effects are noticeable and can cause signal degradation. The typical SI effects of the impedance discontinuity caused by true 3D vias can be seen in the plots in Figure 3.



When simulating a complete channel, signal paths are analyzed using differential vias. Differential vias improve signal integrity, but can also cause signal degradation if the via stubs are not correctly configured. Via stubs not only cause SI issues, they can completely attenuate signals at certain frequencies.

Figure 4 shows analysis on a design with a pair of differential vias on a 16-layer board. The S-parameter plot (Figure 4a) and the eye diagram (Figure 4b) illustrate how via stubs can produce unwanted resonance peaks (8 GHz in the example).



The S-parameter plot shows that the via stubs (red and pink) produce several resonance points, at which point the signal component cannot be transmitted. With the stubs removed (yellow and white), there are no resonance points introduced. Similarly, the eye diagram becomes much smaller with the stubs.

Effects of unused pads. The differential signal paths often enter on one layer and exit on another layer, transmitted between layers through vias. The unused via pads also can cause SI problems. Figure 5 shows the configuration of a pair of vias going through a board stackup of 26 layers. Leaving all these pads in place can cause a resonance peak at lower frequency. By removing the pads, the resonances are pushed upward in frequency, benefiting SI. Backdrilling is the best way to handle these problems, but removing the pads can help the problem when backdrilling is not possible.



Understanding the impacts from 3D structures on signal interconnects is important for designers to ensure good design practice. However, the most common case is to know not only whether there is a design problem, but also how much the effect could be and if a design can still work without significant modification.

To answer these questions, 3D modeling functions are needed to produce detailed results for studying structure behavior and making tradeoffs.

Effectively using 3D modeling. When effectively putting the modeling into practice on an actual circuit, the designer has a number of questions for which he is seeking an answer. Is there an SI problem? If so, what is the magnitude and source of the problem? Can the problem be solved without significant modification, and if not, how much modification is required?

Analysis tools must be capable of answering these questions quickly and accurately. Until recently, 3D analysis of a particular structure has been performed in a separate modeling environment from the general PCB (or package) layout and SI simulation tools. This is adequate for simple structures that can be manually created. But for complex or arbitrary geometries, a standalone tool requires database translation first to get structure geometries imported from layout or port-route analysis environment, which commonly is owned by third parties. In addition, the translation itself can introduce errors during conversion. Conversion can be time-consuming and risky. Also, most tools to date have required that the user have strong electromagnetic experience to use them effectively.

Initial analysis should begin in the pre-layout planning stages. As you could see in the analysis of via stubs, understanding the effects of vias before actually beginning the layout can permit potential problems to be discovered and mitigated before anything has to be unraveled. For this early analysis, it is possible to use a separate 3D tool without much difficulty.

Once pre-layout studies have been completed, the structure is put on board with other nets routed, components placed, and holes drilled. Even so, the resulting PCB layout can still have coupling with some components, and the previously understood behavior can be affected; there may also be new noise sources on the board after layout as well. When this happens, the discontinuity effect from the particular 3D object must be simulated again, including its immediate neighbors, such as nets, other vias, etc. At this stage of development, using a separate 3D tool to analyze the more complicated geometry is very, very tedious.

Better is to have a 3D modeling engine integrated with a general layout and SI environment. The integration then permits detailed structure design/tuning in the pre-layout stage and discontinuity effect verification at port-route level. This solution is illustrated in Figure 6. In this example, Mentor Graphics’ HyperLynx was used first to specify a pair of differential vias in the pre-layout environment (Figure 6a) and determine if a single stitching (or ground) via is sufficient for the required switching rate.



After layout, the designer can select the interested area in the routed design where other nets and structures have been placed near the vias of interest, and tell the tool to export the piece of arbitrary geometry to the 3D modeling engine for creation of proper 3D model (Figure 6b). The resulting model (Figure 6c) highlights the coupling effect to the pre-defined differential via structure. Because the position of geometry cut on the board is known, the 3D model can be connected back to the interested nets in channel simulation. Armed with these data, the designer can then decide if the channel budget can tolerate the effect, or if more design work is necessary to reduce the extra noise.

Dr. Zhen Mu is a product market manager at Mentor Graphics (mentor.com), responsible for signal integrity and power integrity products for printed circuit board and package analysis.

The window to identify and train the next generation of designers is closing. What we can do about it.

Read more: PCB Designers, Rev. 2

大手PCB/EMS企業が、ODB++で作業時間の短縮と品質改善を実現

ビアシステムズのプリント基板(PCB)製造部門(本社: 米国オレゴン州フォレスト・グローヴ)は、PCB設計企業との間で、設計データを製造企業へ渡すためのフォーマットとして「ODB++」の採用が遅々として進まない状況に頭を抱えています。従来手法ままでは、製造部門側で設計パッケージをインポートして解析し、製造側のツールで使えるよう準備するのに長い時間がかかってしまうという問題があるのです。ODB++ファイルを完全活用することで、時間がかかる手作業を大幅に削減し、品質関連エラーの発生頻度を減らすことができます。

設計側と製造側にとってのODB++のメリットは、設計側から「製造可能な設計データ」を渡せるため、製造側の負担が軽減されることにあります。「製造可能な設計データ」と「インテリジェントなデータ」を一緒に送ることにより、最短のサイクルタイムで製造が可能になり、新製品導入(NPI)時の品質も大幅に改善されます。

ビアシステムズの顧客である設計企業の大半が、GerberExcellon、ネットリスト・ファイルに加えて別途図面や仕様書で製品データを渡しています。1980年から使用されているGerberフォーマットは、PCBの製造に必要な情報の多くを含む一方、重大な欠落データもあります。例えば、穴あけ情報はGerberファイルに含まれていないので、別のフォーマット(通常Excellon)のファイルで渡さなければなりません。さらに、PCBの層構成やネットに関する情報も、Gerberファイルには含まれていません。これらの情報はすべて別のファイルや文書で渡されるため、製造側は受け取った後にデータを再統合しなければなりません。しかも最近は、埋込みビアやブラインド・ビア、複雑なシーケンシャル積層法の使用が進み、表面仕上げの多様化ともあいまって、このCAD/CAMデータ交換の問題が深刻化しています。GerberExcellon、ネットリストなど従来のフォーマットでは対応できない問題へと発展しているのです。

Gerberファイルを製造で使える形のデータセットに変えるには、大規模な手作業が必要です。製造側は、ファイルを11つマニュアルで精査し、層構成のレイヤをどのように適合させるかを確認します。加えて、Gerberファイルを使うと、構文エラーや丸めによる精度の誤差の発生が頻発します。Gerberファイルと、穴あけ情報/ネットリスト・ファイル、文書の情報から、正しいPCB仕様を抽出するには多大な労力が必要なのです。

完全に定義されたフォーマットを使うこと、ツールがフォーマットに対応していること、顧客への導入を支援し、フォーマットの有効性を保証してくれる組織があること、などが成功の鍵です。ODB++フォーマットを使用すると、必要なデータすべてを製造側に渡すことができます。ODB++ファイルには、基板の層構成情報だけでなく、穴あけ、マスク、ネットの情報やインテリジェントな属性が広く含まれ、別途図面などでデータを渡す必要がなくなります。製品に関するあらゆる製造レベルの定義が、必要な情報すべてがそろった形で1つのファイル構造に入ります。1は、Gerberデータの代わりにODB++データを製造側に渡すメリットを示しています。FMEA(故障モード影響度解析)の観点から見ると、ODB++の機能をフル活用することにより、製品用PCBの品質も改善できます。

 


1. 従来、製造側に渡していたデータセットは、多くのマニュアル処理が必要でした。各ステップでエラーが発生しやすく、不必要なリスクをPCB製造プロセスへ持ち込んでいました。ODB++の高度な機能を活用すれば、実質すべてのステップを電子的に実行して、低リスクで高品質のデータセットを生成できます。

 

完全なODB++ファイルセットを渡さないと、ODB++フォーマットの自動機能を最大活用できない点に留意してください。これは、DFM(製造性考慮設計)解析とDFMルールの準拠を含めた完全なデータ交換プロセスを実行することで実現します。また、適切な属性すべてのやり取りも、ファイルセットに含めなければいけません。製造側へ部分的なファイルセットしか渡さない場合、ODB++が提供する高度なインテリジェントな機能を活用することはできません。完全なファイルセットを定義したら、単一の.tgzファイルに圧縮して製造側へ渡します。この.tgzファイルを製造ソフトウェアが自動認識し、ファイル構造を読み込んでファイルの処理方法を判断します。

ビアシステムズでは、Gerberデータを使用する場合、製造現場ですぐに使用可能なデータセットを生成するためだけに、マルチステップのワークフローを実行しなければなりません。まず、すべてのGerberファイルをマニュアルで精査して必要なデータがすべて含まれているかどうかを確認し、次にデータの精度と解像度が、PCBの製造に十分であるかを検証します。その後、製造を進めるために手作業でデータの「リバース・エンジニアリング」を行い、基板の層を再構成しなければなりません。穴あけ仕様のデータを統合して、再度精度チェックする必要もあります。また、ソルダーマスクやシルクスクリーンのデータも取り込まなければなりません。

ワークフローのどの時点でも、エラーやデータ抜けが発生する可能性があります。エラーやデータ抜けが発生すると、エラー修正や追加データ取得のために何度も設計側とやり取りする必要が出てきます。平均すると、渡されたデータ・パッケージの約25%が以下の問題を抱えています。

  • レイヤ情報、製造図面、穴あけ情報のファイルなどの不足
  • ネットリストのフォーマット違反
  • ネットリスト例外違反

「他のどのようなフォーマットよりODB++が優れている」との主張を裏付けるデータがビアシステムズには数多く蓄積されています。標準Gerberデータを使った入力の場合、インポートして解析し、製造CAMツールで使用可能なデータを準備するだけで12時間かかります。ODB++の登場から数年たっていますが、いまだに設計企業や製造企業の多くは、ODB++の高度な機能を活用し切っていません。例えば、自動化を進めて手作業の削減を可能にする多くの属性が利用可能であるにもかかわらず、それらをファイルに含めることができていません。設計の複雑度によりますが、インテリジェントな属性を含めたODB++ファイルを渡すことでCAM作業前の準備時間を大幅に短縮できます。ODB++は単一のファイルにインテリジェントな属性と必要なデータをすべて含めたデータ・パッケージです。1は、ビアシステムズにおいて、Gerberを使用した場合とODB++を使用した場合との作業時間短縮と品質改善(FMEA)を比較したものです(表1のデータはODB++1とする)。

 

1. ビアシステムズにおけるCAM前準備時間の比較

 

2. 目で見るGerberデータとODB++データの比較(左: Gerberデータ、右: クリーンなODB++データ)

 

ビアシステムズでは、製造プロセス全体を考慮した場合、Gerberデータと比較してODB++データには以下のメリットがあると考えています。

  • Gerberデータと比べてインポート/エクスポート診断を大幅に短縮できる
  • プロセスの初期段階でエラーを特定し設計側に伝達できる
  • Gerberデータで頻発するフォーマット・エラーやネット例外がなくなる
  • 製造側は、設計側が実際に使用したネット名を見ることができるため、プロセスを簡素化できる
  • ポジティブ・プレーンに対応するために必要となるデータが減る

PCB顧客側のメリット

ODB++データ・フォーマットの使用は、PCB製造企業だけではなく設計企業にとっても大きなメリットがあります。コストと設計時間が大幅に削減でき、その結果、製品をより早く市場に出すことができます。さらに、PCB顧客側のリスクも大幅に低減します。高品質のデータが製造企業へ渡されるためリスクが低減し、PCB実装にも良い影響をもたらすからです。

ビアシステムズでは、収集したデータに基づいて、「検証済みの完全なODB++ファイルを受け渡すことで、NPIにおけるエラーのリスクは5分の1に減る」と結論づけました。ODB++使用のメリットはほかにもあります。以下は、PCB設計企業の観点から見たODB++使用のメリットです。

  1. 全体として、製造と実装におけるエラー発生のリスクが低減する
  2. インテリジェントなデータを渡すため、完成したPCBを期日通りに納入できる確率が高まる
  3. エラーを修正したり、ファイルが見つからないためにデータセットを再送信したりする時間が減る
  4. 不正なデータが製造側に送られて拒否され、時間的/経済的損失が発生する可能性が減る
  5. 不正なファイル定義(層構成のエラーや極性エラー)が発生する頻度が減る
  6. Gerberで頻出する穴あけパターン不整合の問題が解消する
  7. 製造/実装エンジニアから素早いフィードバックが得られ、迅速にエラーが解決する

ビアシステムズは経験上PCB設計企業がODB++ファイルによる情報伝達へ移行するのは非常に簡単だと考えています。主要なPCB設計ソフトウェア・ツールのほとんどが、ODB++出力に対応しています。PCB設計企業の大多数が、製造企業にデータを送る前に、生成したODB++ファイルを視覚的に確認するツールを持っていることも分かりました。概してこれらのツールは、既存のどのGerberビューアよりも包括的で使い勝手が良くなっています。

以下のツールをはじめ、設計から製造のエコシステム内で使用されるCAD/CAMツールの大半がODB++に対応しています。

CAD: 図研、ケイデンス、メンター・グラフィックス、アルティウム、Intercept
製造CAM: フロントライン、UCAMCOWISEDownstreamGraphiCode
実装CAM: メンター・グラフィックス、シーメンスPLMAegis、フジコミュニケーション、AssembléonUniversal Instruments、名古屋電機工業

メンター・グラフィックスのOpenDoorプログラムでは、すべてのCADツール・サプライヤが無料でODB++フォーマットにアクセスできます。メンター・グラフィックスは引き続き、完全オープン・フォーマットとしてODB++をサポートします(図3。また、ODB++の開発を推進し、さらにインテリジェントな機能を近く追加する予定です。ビアシステムズをはじめとする製造企業と協働し、ODB++の将来に向け新たな拡張機能を開発します。

 


3. ODB++ビューアで、ODB++データ・パッケージ全体を包括的に把握できます。ODB++ビューアは、odb-sa.comから無料で入手可能です。

 

IPを送ることに関する懸念

設計企業の中には、IPを製造企業へ送ることを懸念している企業もあります。実際ビアシステムズでは、リバース・エンジニアリングを行ったデータが実質的にODB++ファイルと同じ情報という結果を得ていますが、設計企業から真のIPを取得することはありません。現在ビアシステムズは、データ・パッケージの約10%ODB++フォーマットで受け取っており、その多くは自動化やサイクルタイム短縮のメリットをもたらすインテリジェントな属性を含んでいません。しかし、ODB++に移行した多くの設計企業が、移行がもたらした結果とコスト削減に満足しています。

 

Kent Balius is vice president, global front end engineering, and Stephan Hackl is CAM lead at Viasystems (viasystems.com). Julian Coates is director of business development, Valor Division, Mentor Graphics (mentor.com).

A March earthquake. September floods. Social unrest. Throughout 2011, upheaval was in the air.

Acquisitions, bankruptcies and Mother Nature were the name of the game in 2011, as topsy-turvy market conditions coupled with inexplicable environmental disasters and unprecedented social backlash led to what were in some cases previously inconceivable opportunities.

In what will remain a year for the books, an earthquake and subsequent tsunami hit northeastern Japan, wiping out scores of manufacturing plants and other business, and leaving painful images of the dead. But in what turned out to be Japan’s finest hour, the nation recovered quickly, with most multinational business back to normal within two quarters. Thailand wasn’t so fortunate. Plants there took such a drubbing that it could be a year before they are usable again. Worse, the repeat disasters had decision-makers rethinking their supply-chain plans.

Had it not been for the weather, the story of the year would have been Elcoteq. Once a top 5 EMS company, the onetime main supplier to Nokia found the competition from Foxconn too much to overcome. It saw sales and profits spiral down over a five-year span, then finally declared bankruptcy last fall, shuttering or selling all but four of its 13 manufacturing sites.



Watching, and perhaps learning from, Elcoteq’s mistakes, No. 2 Flextronics bailed from the price-sensitive PC assembly space in 2011. Having just formally entered the PC production business in 2008, Flextronics quickly grew that segment to $4 billion in annual revenue, only to see margin erosion threaten to wipe out the company’s profits. Competing in a commodity space works only for the largest player, it seems.

Speaking of the largest player, Foxconn (who else?) in 2011 continued its long reign at the top of the pile. It seems hard to imagine, but 10 years ago, Foxconn trailed Flextronics, Solectron, Sanmina-SCI and Celestica in annual revenues. Still, cracks in its formidable armor began to show. Dinged by government-mandated wage hikes, Foxconn has moved much of its reportedly 800,000-man workforce inland, leaving its Shenzhen campus to Apple (more on that in a moment). Worldwide social pressures shone an uncomfortable spotlight on Foxconn, where a blitzkrieg of worker suicides, plant explosions, inflammatory statements (and, perhaps, just a little bit of Apple fatigue) put the firm squarely in the crosshairs of the mainstream media, not to mention several workers’ rights NGOs. In response, Foxconn intimated plans to automate a number of its operations with robots.

Upheaval. An army of robots would have made no difference in Thailand, which was turned upside down when fall floods like none seen in the country in 50 years soaked the nation for the better part of two months. No EMS company was decimated more than Fabrinet, No. 19 on the 2010 list and headed for an even higher ranking. High waters breached two of its facilities, rendering one permanently closed and taking the other offline for months. Others that felt the impact in Thailand included No. 6 Cal-Comp, No. 7 Benchmark, No. 42 Hana Microelectronics and No. 47 SVI Public Co.

No. 14 Beyonics also was hit hard by the Thailand floods. Having seen sales fall about 15% over the past two years, and in the midst of five straight unprofitable quarters, the Singapore-based firm in October announced plans to go private. (The company should know something about going private; its founders came from Flextronics, which did the same thing in 1987 before relisting in 1991.)

[Ed.: To see Table 2, the list of the Top 50 EMS companies, click here. To enlarge the table, right-click on it, then click View Image, then left-click on the table.)

In the aftermath of Japan and Thailand, certain OEMs and EMS companies are rethinking their supply chains. No. 3 Jabil already has made clear it wants to navigate away from the all-in-one industrial parks – where suppliers sit almost on top of each other – so characteristic of the Pacific Rim. Moreover, as companies become more aware of time-to-market and the amounts of capital tied up in product in transit from distant lands, a trend is emerging toward positioning production closer to the point of end-use, a phenomenon known in the US as “reshoring.” Social pressures, accented by the long and loud protests over alleged worker exploitation that have landed Foxconn (and its leading customer, Apple) on the front page of The Wall Street Journal for all the wrong reasons, are also leading assemblers to contemplate not just higher but politically safer ground.

As usual, major mergers and acquisitions changed the face of the CIRCUITS ASSEMBLY Top 50 list. No. 21 OnCore Manufacturing, a major defense and aerospace supplier, acquired Victron in what was essentially a merger of financial equals. No. 31 Ducommun made the biggest splash in its 157-year history, acquiring LaBarge in June to form a defense electronics powerhouse. No. 16 AsteelFlash bought Catalyst EMS. (Just after the year ended, No. 8 Plexus announced a deal to acquire Kontron Design Manufacturing Services in Penang.)

Falling off the list was EPIQ, which sold a total of five plants in Bulgaria, Czech Republic and Mexico to No. 25 Integrated Microelectronics Inc. Also departing was Surface Mount Technology Holdings (No. 45 in 2010), the Hong Kong-based EMS firm that endured a painful reorganization in 2011. Revenue plunged 38% year-over-year to about $177.6 million. Suffering a similar fate is former Top 50 mainstay Simclar, which has seen sales fall from a high of $400 million in 2006.
Joining the list were several large flex circuit companies whose EMS revenues were previously not properly accounted for. Most flex PCB fabricators also perform assembly, and it is difficult to get an accurate reading of the value of the bare board from the finished assembly. However, based on data from IPC and others, bare flex circuits comprise roughly 40% of the shipment value. Based on such estimates, No. 12 Nippon Mektron (which has at least 11 plants that perform SMT assembly) and No. 28 MFLEX are now represented in the Top 50.

Whither Kaifa? Not making the list: Sichuan Changhong Electric, a huge Chinese entity (35,000 employees) that makes TVs, white goods and other components. While it builds product for several brand name Japanese OEMs, it was impossible to determine just what its EMS/ODM sales were in 2011. Same goes for Aeroflex. We also left off ODMs such as Qisda, Compal, Wistron, BenQ, and others that are essentially OEMs.

Should Shenzhen Kaifa Technology be included in EMS rankings? It’s not an easy question to answer. On revenue alone, perhaps: Kaifa, as the company is known, had sales of over $4 billion last year. Using that gross number would place it squarely between Sanmina-SCI and Cal-Comp in the Top 10.

But there’s more to it than that. Kaifa generates an extraordinary amount of its revenue from making and selling hard disk drives to Seagate. In fact, under most classifications, Kaifa would rank as an ODM, and not just of printed circuit board assemblies.

Then there’s the confusion of what, exactly, “Kaifa” is. The company, which is supposedly traded under the ticker symbol 00021 on the Shenzhen Exchange, has no current listing. However, it is also apparently a subsidiary of China Electronics Corp.

CEC is giant. The conglomerate says its annual revenues topped $8 billion back in 2006, and it employs more than 70,000 workers across some 61 subsidiaries, including 13 listed holding companies. Among them are cellphone and datacom OEM Panda Electronics, computer and TV manufacturer Greatwall Technology, and yes, Kaifa.

It also is state-owned, and operates directly under the administration of China’s central government. Forget, for the moment, how strange it is for what is essentially a government entity to be publicly traded. Consider instead whether a government business can be considered a contract manufacturer, especially in China, where the Communist Party still holds sway over most economic policy and can pick the winners and losers at the drop of a hat. Want to get a government contract? Use a government provider. It becomes hard to distinguish between what is competitive bidding and what is political.

Then there’s the matter of CEC’s financials. They are dense, to be sure. It’s hard to tell what revenue comes from external customers and what is just “padding” from its own pyramid. Among those that can be discerned, Greatwall alone made up $1.6 billion in revenue in 2010. Read the fine print and you’ll see the company has several “deals” in place to buy components and services from other CEC subsidiaries.

So should Kaifa be listed on the CIRCUITS ASSEMBLY Top 50? Because it is next to impossible to know what its true revenue from EMS-related activities is, we say no, while respecting the decision of others to disagree.

EMS is a lopsided business. The CIRCUITS ASSEMBLY Top 50 make up about 87% of the total revenues of the entire electronics outsourcing industry, although that figure admittedly includes a fair percentage of revenue that would properly be classified as ODM work. The industry as a whole reached about $205 billion in sales last year, according to IHS iSuppli.1 (The research firm predicts industry revenue to be flat in 2012.)

The US continues to dominate the Top 10 list, with five of the top eight entries, although we are seeing some minor shifts take place (Table 3). Regionally, the Top 50 remain intact, led by Southeast Asia (16 entries), North America (15) and Europe (12). Japan gained two entries, a reflection of heretofore unacknowledged EMS work. Notable for its lack of entries is Russia, which almost certainly has domestic firms that would qualify, and whose electronics assembly industry was forecast to reach $14 billion in 2010 (55% of which was industrial or military).2 While changes in the rankings have been most common in the middle to lower half of the list, a few firms are threatening to shake up the top. Given their organic growth and acquisition strategy, respectively, Zollner and AsteelFlash look like good bets to break into the Top 10, should any of the current leaders falter.

References

 

1. Mike Buetow, "iSuppli: EMS in for Flat Year," circuitsassembly.com, Feb. 7, 2012.

2. Ivan Pokrovsky, "Electronics Manufacturing in Russia," New Russian Electronics, Business Industry Yearbook, 2008.

Mike Buetow is editor in chief of CIRCUITS ASSEMBLY; This email address is being protected from spambots. You need JavaScript enabled to view it..

 

Ed: For the 2010 Top 50, click here.

For the 2009 Top 50, click here.

 

 

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